UCB1510DB Просмотр технического описания (PDF) - Philips Electronics

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UCB1510DB

AC97 digital modem codec

Philips Electronics 

Philips Semiconductors

12.4 Interrupt request from UCB1510

UCB1510

AC97 digital modem codec

MLNK

BIT_CLK

SDIN

Interrupt request

Fig 9. Setting the SDIN for interrupt request

Interrupt request

is enabled

12.4.1 When BIT_CLK is running

The AClink is active and the interrupt request is transmitted by setting the interrupt bit

of slot 12 in the AClink frame.

If UCB1510 is configured as a primary codec, this is the case when MLNK is set to 0.

If UCB1510 is configured as a secondary codec, this is the case whether MLNK is set

to 0 or 1.

12.4.2 When BIT_CLK is stopped

In order to request an interrupt, the UCB1510 will assert the SDIN pin, if MLNK is set

to 1. BIT_CLK is not needed for this to happen. This applies when UCB1510 is used

as a primary or secondary codec.

If UCB1510 is configured as a primary codec, BIT_CLK is stopped as a result of

MLNK being set to 1.

If UCB1510 is configured as a secondary codec, BIT_CLK is stopped when the

controller shuts down the primary codec. For UCB1510 to generate interrupt while

BIT_CLK is stopped, MLNK has to be set to 1 before BIT_CLK is stopped.

After BIT_CLK is stopped, SDIN will be brought to 0, unless an interrupt asserts it

to 1. It is recommended that a level triggered interrupt detection is used in case the

interrupt request is asserted at the same time BIT_CLK is stopped.

12.5 Wake-up request to the UCB1510

A cold reset will program the registers to their default value and will wake up the

AClink.

When the AClink is not active (no BIT_CLK present), a rising SYNC will cause a

warm reset. If MLNK is set to 1, a rising RESET will also cause a warm reset. After a

warm reset, MLNK will be reset to 0.

9397 750 06856

Preliminary specification

Rev. 01 — 4 February 2000

© Philips Electronics N.V. 2000. All rights reserved.

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