AD7769 Просмотр технического описания (PDF) - Analog Devices
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AD7769 Datasheet PDF : 16 Pages
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AD7769
(VDD = +12 V ؎ 10%; VCC = +5 V ؎ 5%; AGND [DAC] = AGND [ADC] = DGND = 0 V;
DACA, DACB SPECIFICATIONS VBIAS [DAC] = +5 V; VSWING [DAC] = +2.5 V; VOUTA, VOUTB load to AGND [DAC], RL = 5 k⍀,
CL = 100 pF. All specifications TMIN to TMAX1 unless otherwise noted.)
Parameter
J Version A Version Units Conditions/Comments
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
+25°C
TMIN to TMAX
Bias Offset Match
+25°C
TMIN to TMAX
Plus or Minus Full-Scale Error
+25°C
TMIN to TMAX
Plus or Minus Full-Scale Match
+25°C
TMIN to TMAX
ADC to DAC MATCHING
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Intermodulation Distortion (IMD)
ANALOG OUTPUTS
Output Voltage Ranges
VOUTA, VOUTB
DC Output Impedance
Short-Circuit Current
8
*
±1
*
±1
*
Bits
LSB max
LSB max
± 2.0
*
± 2.5
*
LSB max
LSB max
± 2.5
*
± 3.5
*
LSB max
LSB max
± 1.5
*
± 2.0
*
LSB max
LSB max
± 3.5
*
± 4.0
*
LSB max
LSB max
As Per ADC Specifications
See Terminology
Guaranteed Monotonic. See Terminology.
See Terminology
VOUT A to VOUT B
See Terminology
VOUT A to VOUT B
44
*
48
*
55
*
dB min
dB max
dB typ
VOUT = 20 kHz Full-Scale Sine Wave With fSAMPLING = 400 kHz
VOUT = 20 kHz Full-Scale Sine Wave With fSAMPLING = 400 kHz
fa = 18.4 kHz, fb = 14.5 kHz with fSAMPLING = 400 kHz
VBIAS – VSWING or 0.5
VBIAS + VSWING or
VDD –2.0
0.5
*
20
*
V min
V max
Ω typ
mA typ
Whichever Is the Higher
Whichever Is the Lower
DAC REFERENCE INPUTS
Input Voltage Levels
VBIAS (DAC)
VSWING (DAC)
Input Currents
VBIAS (DAC) Input
VSWING (DAC) Input
3/6.8
*
2.0/3.0 *
±2
*
±1
*
AC CHARACTERISTICS2
Voltage Output Settling Time
4
*
Digital-to-Analog Glitch Impulse 30
*
Digital Feedthrough
1
*
V min/max With Respect to AGND (DAC). For Specified Performance.
V min/max With Respect to AGND (DAC). For Specified Performance.
µA max
µA max
µs max Settling Time to Within ± 1/2 LSB of Final Value. Typically 2.5 µs.
nV sec typ See Terminology
nV sec typ See Terminology
LOGIC INPUTS
CS, RD, WR, ADC/DAC,
CHA/CHB, DB0–DB7
Input Low Voltage, VINL
Input High Voltage, VINH
Input Leakage Current
Input Capacitance
CLK
Input Low Voltage
Input High Voltage
Input Leakage Current
DB0–DB7
Input Coding
0.8
*
2.4
*
± 10
*
10
*
0.8
*
2.4
*
± 10
*
Offset Binary
V max
V min
µA max
pF max
V max
V min
µA max
External Clock. For Internal Clock Operation Connect
the CLK Pin to VDD.
POWER REQUIREMENTS
As per ADC Specifications
NOTES
1Temperature range as follows: J Version: 0°C to +70°C; A Version: –40°C to +85°C.
2Sample tested at +25°C to ensure compliance.
*Specifications same as J Version.
Specifications subject to change without notice.
REV. A
–3–
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