TJA1080 Просмотр технического описания (PDF) - NXP Semiconductors.

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TJA1080

FlexRay transceiver

NXP Semiconductors. 

NXP Semiconductors

TJA1080

FlexRay transceiver

7.1.3 Bus activity and idle detection

The following mechanisms for activity and idle detection are valid for node and star

configurations in normal power modes:

• If the absolute differential voltage on the bus lines is higher than Vi(dif)det(act) for

tdet(act)(bus), then activity is detected on the bus lines and pin RXEN is switched to LOW

which results in pin RXD being released:

– If, after bus activity detection, the differential voltage on the bus lines is higher than

VIH(dif), pin RXD will go HIGH

– If, after bus activity detection, the differential voltage on the bus lines is lower than

VIL(dif), pin RXD will go LOW

• If the absolute differential voltage on the bus lines is lower than Vi(dif)det(act) for

tdet(idle)(bus), then idle is detected on the bus lines and pin RXEN is switched to HIGH.

This results in pin RXD being blocked (pin RXD is switched to HIGH or stays HIGH)

Additionally, in star configuration, activity and idle can be detected (see Figure 5 for state

transitions due to activity/idle detection in star configuration):

• If pin TXEN is LOW for longer than tdet(act)(TXEN), activity is detected on pin TXEN

• If pin TXEN is HIGH for longer than tdet(idle)(TXEN), idle is detected on pin TXEN

• If pin TRXD0 or TRXD1 is LOW for longer than tdet(act)(TRXD), activity is detected on

pins TRXD0 and TRXD1

• If pin TRXD0 and TRXD1 is HIGH for longer than tdet(idle)(TRXD), idle is detected on

pins TRXD0 and TRXD1

7.2 Operating modes in node configuration

The TJA1080 provides two control pins STBN and EN in order to select one of the modes

of operation in node configuration. See Table 4 for a detailed description of the pin

signalling in node configuration, and Figure 3 for the timing diagram.

All modes are directly controlled via pins EN and STBN unless an undervoltage situation

is present.

If VIO and (VBUF or VBAT) are within their operating range, pin ERRN indicates error flag.

Table 4. Pin signalling in node configuration

Mode

STBN EN ERRN[1]

LOW

HIGH

Normal

HIGH HIGH error flag error flag

Receive-only HIGH LOW set

reset

Go-to-sleep

Standby

Sleep

LOW

LOW

LOW

HIGH error flag error flag

LOW set[2]

reset

X

RXEN

LOW

bus

activity

HIGH

bus

idle

wake flag wake

set[2]

flag

reset

RXD

LOW

bus

DATA_0

wake flag

set[3]

Transmitter INH1 INH2

HIGH

bus

enabled

DATA_1 disabled

or idle

HIGH HIGH

wake

flag

reset

float[4]

float float

[1] Pin ERRN provides a serial interface for retrieving diagnostic information.

[2] Valid if VIO and VBUF or VBAT are present.

[3] Valid if VIO and VBUF are present.

[4] If wake flag is not set.

TJA1080_2

Product data sheet

Rev. 02 — 12 July 2007

© NXP B.V. 2007. All rights reserved.

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