TFRA08C13 Просмотр технического описания (PDF) - Agere -> LSI Corporation

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TFRA08C13

OCTAL T1/E1 Framer

Agere -> LSI Corporation 

Preliminary Data Sheet

October 2000

TFRA08C13 OCTAL T1/E1 Framer

Pin Information (continued)

Table 2. Pin Descriptions (continued)

E3

RCRCMFS[1] O Receive Framer CRC-4 Multiframe Sync. This active-high signal is

P3

RCRCMFS[2]

AB4

RCRCMFS[3]

the CEPT CRC-4 multiframe synchronization pulse in the receive

framer.

AD16

RCRCMFS[4]

AB23

RCRCMFS[5]

R24

RCRCMFS[6]

B23

RCRCMFS[7]

A10

RCRCMFS[8]

C1

TSSFS[1]

O Transmit Framer Signaling Superframe Sync. This signal is the

M3

TSSFS[2]

AA1

TSSFS[3]

CEPT signaling superframe (multiframe) synchronization pulse in the

transmit framer. This signal is active-high.

AD11

TSSFS[4]

AA26

TSSFS[5]

N24

TSSFS[6]

A22

TSSFS[7]

A8

TSSFS[8]

C2

TCRCMFS[1] O Transmit Framer CRC-4 Multiframe Sync. This signal is the CEPT

N1

TCRCMFS[2]

Y4

TCRCMFS[3]

CRC-4 submultiframe synchronization pulse in the transmit framer. This

signal is active-high.

AF12

TCRCMFS[4]

Y25

TCRCMFS[5]

M26

TCRCMFS[6]

B21

TCRCMFS[7]

C9

TCRCMFS[8]

AF9

MPMODE

Iu MPMODE. Strap to ground to enable the Motorola 68360 microproces-

sor protocol (MODE1). Strap to VDD to enable the Intel 80X86/88 micro-

processor protocol (MODE3).

U26

RD_R/W

I Read (Active-Low). In the Intel interface mode, the TFRA08C13 drives

the data bus with the contents of the addressed register while RD is

low. Read/Write. In the Motorola interface mode, this signal is asserted

high for read accesses; this pin is asserted low for write accesses.

* Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

‡ Asserting this pin low will initially force RDY to a low state.

LLuucceenntt TTeecchhnnoollooggiieess IInncc..

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