TFRA08C13 Просмотр технического описания (PDF) - Agere -> LSI Corporation

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TFRA08C13

OCTAL T1/E1 Framer

Agere -> LSI Corporation 

Preliminary Data Sheet

October 2000

TFRA08C13 OCTAL T1/E1 Framer

Pin Information (continued)

Table 2. Pin Descriptions (continued)

Pins

Symbol Type*

Description

F3

T1

AF2

AD17

AC25

T24

D24

A11

G4

R3

AD2

AE18

AC24

P25

A25

D12

F2

T2

AB3

AC17

AC26

RFRMCK[1]

RFRMCK[2]

RFRMCK[3]

RFRMCK[4]

RFRMCK[5]

RFRMCK[6]

RFRMCK[7]

RFRMCK[8]

RFRMDATA[1]

RFRMDATA[2]

RFRMDATA[3]

RFRMDATA[4]

RFRMDATA[5]

RFRMDATA[6]

RFRMDATA[7]

RFRMDATA[8]

RFS[1]

RFS[2]

RFS[3]

RFS[4]

RFS[5]

O Receive Framer Clock. Output receive framer clock signal used to

clock out the receive framer output signals. In normal operation, this is

the recovered receive line clock signal.

O Receive Framer Data. This signal is the decoded data input to the

receive elastic store. During loss of frame alignment, this signal is

forced to 1.

O Receive Frame Sync. This active-high signal is the 8 kHz frame syn-

chronization pulse generated by the receive framer. During loss of

frame alignment and signaling superframe or multiframe alignment, this

signal is forced to 0.

R23

RFS[6]

B24

RFS[7]

B10

RFS[8]

E4

R2

AC2

AE17

RFDLCK[1]

RFDLCK[2]

RFDLCK[3]

RFDLCK[4]

O Receive Facility Data Link Clock. In DS1-DDS with data link access,

this is an 8 kHz clock signal. Otherwise, this is a 4 kHz clock signal. The

receive data link bit changes on the falling edge of RFDLCK.

AB24

N25

C23

RFDLCK[5]

RFDLCK[6]

RFDLCK[7]

D10

RFDLCK[8]

* Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

‡ Asserting this pin low will initially force RDY to a low state.

LLuucceenntt TTeecchhnnoollooggiieess IInncc..

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