TFRA08C13 Просмотр технического описания (PDF) - Agere -> LSI Corporation

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TFRA08C13

OCTAL T1/E1 Framer

Agere -> LSI Corporation 

Preliminary Data Sheet

October 2000

TFRA08C13 OCTAL T1/E1 Framer

Pin Information (continued)

Table 2. Pin Descriptions (continued)

Pins

Symbol Type*

Description

D2

P2

Y3

AE13

AA24

TFS[1]

TFS[2]

TFS[3]

TFS[4]

TFS[5]

O Transmit Framer Frame Sync. This signal is the 8 kHz frame synchro-

nization pulse in the transmit framer. This signal is active-high.

M25

TFS[6]

C22

TFS[7]

B8

TFS[8]

B1

TFDLCK[1]

O Transmit Facility Data Link Clock. In DS1-DDS with data link access,

M4

TFDLCK[2]

AA2

TFDLCK[3]

this is an 8 kHz clock signal; otherwise, 4 kHz. The transmit frame

latches data link bits on the falling edge of TFDLCK.

AE12

Y26

L25

TFDLCK[4]

TFDLCK[5]

TFDLCK[6]

D20

TFDLCK[7]

B7

B3

N2

W3

AF11

Y24

TFDLCK[8]

TFDL[1]

TFDL[2]

TFDL[3]

TFDL[4]

TFDL[5]

I Transmit Facility Data Link. Optional serial input facility data link bit

stream inserted into the transmit line data stream by the transmit

framer. In DS1-DDS with data link access, this is an 8 kbits/s signal;

otherwise, 4 kbits/s. In the CEPT frame format, TFDL can be pro-

grammed to one of the XSa bits of the NOT FAS frame time slot 0.

M24

TFDL[6]

C21

TFDL[7]

D8

TFDL[8]

C5

L3

Y1

AD10

RCHIDATA[1]

RCHIDATA[2]

RCHIDATA[3]

RCHIDATA[4]

I Receive CHI Data. Serial input system data at 2.048 Mbits/s,

4.096 Mbits/s, or 8.192 Mbits/s.

W25

L26

A21

RCHIDATA[5]

RCHIDATA[6]

RCHIDATA[7]

A7

RCHIDATA[8]

* Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

‡ Asserting this pin low will initially force RDY to a low state.

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