(8K x 16-Bit) Dual Port RAM High-Speed CMOS
FIGURE 12. 32-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
7025E
1. No arbitration in Master/Slave. BUSY - IN inhibits write in Master/Slave.
FIGURE 13. TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE 1
1. CS = VIH for the duration of the above timing (both write and read cycle).
1000586
12.19.01 Rev 2
All data sheets are subject to change without notice 16
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