STK6005 Просмотр технического описания (PDF) - Unspecified

Номер в каталоге

Компоненты Описание

производитель

STK6005

Flat Panel Scaler

Unspecified 

VCLK

Cref

Y(RIN)

UV(GIN)

Hsync/Vsync

/Field

Href/Vref

STK6005

Y0

Y1

Y2

U0

V0

U2

YUV16 input format timing diagram

5.2 Output Timing and Format

The output interface consists of two pixel ports, each containing Red / Green / Blue in colors with 6 or 8

bits of resolution. There are three output control signals for panel – PVS, PHS and PDE. The output

pixels and control signals above are all synchronous to the active edge of panel output clock DCLK. The

polarity of output clock / control signals and the timing of the active edge of output clock are

programmable by setting the internal registers.

There are two output formats – single / dual pixels output modes. In single pixel output mode, pixel data

are output from PE_R/G/B ports only, and the PO_R/G/B ports are disabled. In dual pixel output mode,

pixel data are output to both PE_R/G/B and PO_R/G/B ports in parallel. The first pixel of a line will be

output to PE_R/G/B ports and the second pixel will be output to PO_R/G/B ports.

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