STK6005 Просмотр технического описания (PDF) - Unspecified

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STK6005

Flat Panel Scaler

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STK6005

HSR = horizontal input display resolution / output display resolution * 32768

VSR = vertical input display resolution / output display resolution * 32768

This chip provides 6 advanced filters to get a high quality-scaling image for requirements on different

sharpness. Set EnFilt flag to 1 to enable scaling function using the filter defined by FiltType register.

5.8 Operating Mode

STK6005 uses internal line buffers to perform the scaling function. Since there is no external frame buffer

serving as a frame rate converter, the output vertical frequency is always equal to the input vertical frequency

during normal operation. The period of PCLK should be programmed as close as the formula listed below to

avoid over-run / under-run conditions of internal line-buffers.

Period of PCLK = Period of VCLK * RateH * RateV

where

RateH = total pixels of an input line / total pixels of an output line

RateV = total input lines / total output lines

= total input display lines / total output display lines

STK6005 provides three operating modes to synchronize the input and output display timing:

1. Free-run mode:

EnSyncH {0x3D[7]} = 0

EnSyncV {0x3D[6]} = 0

In this mode, there is no timing relationship between the input and output timing. Registers PHT and

PVT control the output horizontal period and vertical period respectively. For this mode, even if no input

signal comes, the output timing can also be generated automatically. This mode is used when there is no

valid input or used for testing purpose.

2. Synchronization to Input V-Sync:

EnSyncH {0x3D[7]} = 0

EnSyncV {0x3D[6]} = 1

In this mode, the input vertical timing has impacted on the output vertical timing. The input V-Sync

leading edge will generate a locking event to lock the output display timing. Therefore, the output vertical

period will keep the same as the input vertical period. The latency between the input V-Sync leading edge

and the locking event can be programmed through registers DlyLine and DlyPxl. The output horizontal

period is set by PHT. The PVT value should be set to maximum (0x7FF) value for this mode. For the

advantage of this mode, all output horizontal periods are equal. For the disadvantage of this mode, when

some errors occur in the real output video clock (PCLK) and in the ideal output video clock (VCLK *

RateH * RateV), the buffer overrun or underrun may happen internally due to the accumulation of errors.

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