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SST37VF010-70-3C-NHE Просмотр технического описания (PDF) - Silicon Storage Technology

Номер в каталоге
Компоненты Описание
производитель
SST37VF010-70-3C-NHE
SST
Silicon Storage Technology SST
SST37VF010-70-3C-NHE Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
AC CHARACTERISTICS
Data Sheet
TABLE 9: Read Cycle Timing Parameters VDD = 2.7-3.6V (TA = 0°C to +70°C (Commercial))
SST37VF512-70
SST37VF010-70
SST37VF020-70
SST37VF040-70
Symbol Parameter
Min
Max
Units
TRC
Read Cycle Time
70
ns
TCE
Chip Enable Access Time
70
ns
TAA
Address Access Time
70
ns
TOE
Output Enable Access Time
35
ns
TCLZ1
TOLZ1
CE# Low to Active Output
OE# Low to Active Output
0
ns
0
ns
TCHZ1
CE# High to High-Z Output
25
ns
TOHZ1
TOH1
OE# High to High-Z Output
Output Hold from Address Change
25
ns
0
ns
T9.3 1151
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: Program/Erase Cycle Timing Parameters VDD = 2.7-3.6V (TA = 25°C±5°C)
Symbol Parameter
Min
TBP
Byte-Program Time
TCES
CE# Setup Time
1
TCEH
CE# Hold Time
1
TAS
Address Setup Time
1
TAH
Address Hold Time
1
TDS
Data Setup Time
1
TDH
Data Hold Time
1
TPRT
OE# Rise Time for Program and Erase
50
TVPS
OE# Setup Time for Program and Erase
1
TVPH
OE# Hold Time for Program and Erase
1
TPW
WE# Program Pulse Width
15
TEW
WE# Erase Pulse Width
100
TVR
OE#/A9 Recovery Time for Erase
1
TART
A9 Rise Time to 12V during Erase
50
TA9S
A9 Setup Time during Erase
1
TA9H
A9 Hold Time during Erase
1
Max
20
25
200
Units
µs
µs
µs
µs
µs
µs
µs
ns
µs
µs
µs
ms
µs
ns
µs
µs
T10.1 1151
©2006 Silicon Storage Technology, Inc.
7
S71151-07-000
8/06

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