SAA3323 Просмотр технического описания (PDF) - Philips Electronics

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SAA3323

Drive processor for DCC systems

Philips Electronics 

Philips Semiconductors

Drive processor for DCC systems

Preliminary specification

SAA3323

Table 3 RAM settings by register SET3.

RAM

RTYPE 0

RTYPE 1

RTim 0

RTim 1

REGISTER SET3

bit 0

bit 1

bit 2

bit 3

TFE DATA STREAMS

The TFE module has three read/write data streams that

are accessible via the L3 interface and they are shown in

Table 4.

Table 4 TFE data streams.

DATA STREAM NAME

SYSINFO

AUXINFO

Scratch pad RAM

READ/WRITE

R/W

R/W

R/W

TFE ‘COMMANDS’

These are the commands that need to be sent to the TFE

in order to access the indirectly accessible registers and

the data streams, see Table 5.

Table 5 TFE commands.

NAME

RDSPEED

LDSET0

LDSET1

LDSET2

LDSET3

LDSPDDTY

LDBYTCNT

LDRACCNT

RDAUX

RDSYS

RDDRAC

RDWDRAC

WRAUX

WRSYS

WRDRAC

WRWDRAC

COMMAND BYTE

76543210

EXPLANATION

0 0 0 0 0 0 0 0 read SPEED register

0 0 0 1 0 0 0 0 load new TFE settings register 0

0 0 0 1 0 0 0 1 load new TFE settings register 1

0 0 0 1 0 0 1 0 load new TFE settings register 2

0 0 0 1 0 0 1 1 load new TFE settings register 3

0 0 0 1 0 1 0 1 load SPDDTY register

0 0 0 1 0 1 1 1 load BYTCNT register

0 0 0 1 1 0 0 0 load RACCNT register

0 0 1 0 0 0 0 0 read AUXILIARY information

0 0 1 0 0 0 0 1 read SYSINFO

Y Z 1 0 0 0 1 0 read RAM data bytes (8 bits) from quarter YZ

Y Z 1 0 0 0 1 1 read RAM data words (12 bits) from quarter YZ

0 0 1 1 0 0 0 0 write AUXILIARY information

0 0 1 1 0 0 0 1 write SYSINFO

Y Z 1 1 0 0 1 0 write RAM data bytes (8 bits) to quarter YZ

Y Z 1 1 0 0 1 1 write RAM data words (12 bits) to quarter YZ

Digital equalizer module

The digital equalizer module has 2 basic modes of

operation as shown in Table 6.

Table 6 Basic modes of equalizer module.

MODE

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EXPLANATION

main data and AUX channels are

equalized

only AUX channel is processed; AUX

envelope information is processed

DIGITAL EQUALIZER REGISTERS

The digital equalizer module has 9 write only, 3 read only

and 1 read/write register(s) that are accessible via the

L3 interface, one write register (CMD) and 2 read registers

(STATUS0 and STATUS1) which are directly addressable,

the other registers are indirectly addressable via

commands sent to the CMD register. The registers are

named as shown in Table 7.

May 1994

10

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