SAA3323 Просмотр технического описания (PDF) - Philips Electronics

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SAA3323

Drive processor for DCC systems

Philips Electronics 

Philips Semiconductors

Drive processor for DCC systems

Preliminary specification

SAA3323

Table 7 Digital equalizer register names.

REGISTER NAME

CMD

STATUS0

STATUS1

COEFCNT

FCTRL

CHT1SEL

CHT2SEL

ANAEYE

AEC

SSPD

INTMASK

DEQ2SET

CLKSET

READ/WRITE

W

R

R

W

W

W

W

W

R/W

R

W

W

W

DATA STREAMS

The digital equalizer module has one write only and one

read only data stream that are accessible via the

L3 interface and they are shown in Table 8.

Table 8 Digital equalizer data streams.

DATA STREAM NAME

FIR coefficients to buffer bank

FIR coefficients from active bank

READ/WRITE

W

W

DIGITAL EQUALIZER “COMMANDS”

These are the commands that need to be sent to the digital

equalizer in order to access the indirectly accessible

registers and the data streams.

Table 9 Digital equalizer commands.

NAME

WRCOEF

RDCOEF

LDCOEFCNT

LDFCTRL

LDT1SEL

LDT2SEL

LDTAEYE

LDAEC

RDAEC

RDSSPD

LDINTMSK

LDDEQ3SET

LDCLKSET

COMMAND BYTE

76543210

EXPLANATION

0 0 1 1 0 0 0 0 write FIR coefficients to the digital equalizer buffer bank

0 0 1 0 0 0 0 0 read FIR coefficients from the digital equalizer active bank

0 0 0 1 0 0 1 1 load FIR coefficient counter

0 0 0 1 0 1 0 0 load filter control register

0 0 0 1 0 1 1 0 load CHTST1 pin selection register

0 0 0 1 0 1 1 1 load CHTST2 pin selection register

0 0 0 1 1 0 0 0 load ANAEYE channel selection register

0 0 0 1 1 0 0 1 load AEC counter

0 0 1 0 0 0 1 0 read AEC counter

0 0 1 0 0 1 0 0 read SEARCH speed register

0 0 0 1 0 0 1 0 load interrupt mask register

0 0 0 1 0 0 0 0 load digital equalizer settings register

0 0 0 1 0 0 0 1 load PLL clock extraction settings register

Table 10 Filter control register.

BIT

Meaning

Default

7

6

5

4

3

2

1

0

−

−

−

µCS(1)

SH1

SH0

Reserved

0

0

0

0

1

0

1

1

Note

1. µCS is a microcontroller controlled coefficient bank switch. This causes the filter coefficients to be activated at a time

that is safe for the digital equalizer, i.e. at the end of the FIR program and that the complete value of coefficient

number 9 has been received.

May 1994

11

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