R5F7146 Просмотр технического описания (PDF) - Renesas Electronics

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R5F7146

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Renesas Electronics 

5.5.1 Types of Exceptions Triggered by Instructions ...................................................... 85

5.5.2 Trap Instructions ..................................................................................................... 85

5.5.3 Illegal Slot Instructions ........................................................................................... 86

5.5.4 General Illegal Instructions..................................................................................... 86

5.6 Cases when Exceptions are Accepted .................................................................................. 87

5.7 Stack States after Exception Handling Ends ........................................................................ 88

5.8 Usage Notes ......................................................................................................................... 90

5.8.1 Value of Stack Pointer (SP) .................................................................................... 90

5.8.2 Value of Vector Base Register (VBR) .................................................................... 90

5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling .......... 90

5.8.4 Notes on Slot Illegal Instruction Exception Handling ............................................ 91

Section 6 Interrupt Controller (INTC) .................................................................93

6.1 Features................................................................................................................................ 93

6.2 Input/Output Pins ................................................................................................................. 95

6.3 Register Descriptions ........................................................................................................... 96

6.3.1 Interrupt Control Register 0 (ICR0)........................................................................ 97

6.3.2 IRQ Control Register (IRQCR) .............................................................................. 98

6.3.3 IRQ Status register (IRQSR) ................................................................................ 100

6.3.4 Interrupt Priority Registers A, D to F, and H to L

(IPRA, IPRD to IPRF, and IPRH to IPRL)........................................................... 103

6.4 Interrupt Sources................................................................................................................ 106

6.4.1 External Interrupts ................................................................................................ 106

6.4.2 On-Chip Peripheral Module Interrupts ................................................................. 107

6.4.3 User Break Interrupt ............................................................................................. 107

6.5 Interrupt Exception Handling Vector Table....................................................................... 108

6.6 Interrupt Operation............................................................................................................. 111

6.6.1 Interrupt Sequence ................................................................................................ 111

6.6.2 Stack after Interrupt Exception Handling ............................................................. 114

6.7 Interrupt Response Time.................................................................................................... 114

6.8 Data Transfer with Interrupt Request Signals .................................................................... 116

6.8.1 Handling Interrupt Request Signals as Sources

for DTC Activation and CPU Interrupts ............................................................... 117

6.8.2 Handling Interrupt Request Signals as Sources

for DTC Activation, but Not CPU Interrupts........................................................ 117

6.8.3 Handling Interrupt Request Signals as Sources

for CPU Interrupts, but Not DTC Activation........................................................ 118

6.9 Usage Note......................................................................................................................... 118

Rev. 3.00 May 17, 2007 Page xi of xliv

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