R5F7146 Просмотр технического описания (PDF) - Renesas Electronics
Номер в каталоге
Компоненты Описание
производитель
R5F7146 Datasheet PDF : 1022 Pages
| |||
9.4 Register Descriptions......................................................................................................... 205
9.4.1 Common Control Register (CMNCR) .................................................................. 205
9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 and 1) .................................. 207
9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 and 1)................................ 210
9.4.4 Bus Function Extending Register (BSCEHR) ...................................................... 212
9.5 Operation ........................................................................................................................... 216
9.5.1 Endian/Access Size and Data Alignment.............................................................. 216
9.5.2 Normal Space Interface ........................................................................................ 218
9.5.3 Access Wait Control ............................................................................................. 222
9.5.4 CSn Assert Period Extension ................................................................................ 224
9.5.5 Wait between Access Cycles ................................................................................ 225
9.5.6 Bus Arbitration ..................................................................................................... 228
9.5.7 Others.................................................................................................................... 232
9.5.8 Access to On-Chip FLASH and On-Chip RAM by CPU ..................................... 233
9.5.9 Access to On-Chip Peripheral I/O Registers by CPU........................................... 233
9.5.10 Access to External Memory by CPU .................................................................... 235
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)................................... 239
10.1 Features.............................................................................................................................. 239
10.2 Input/Output Pins............................................................................................................... 245
10.3 Register Descriptions......................................................................................................... 246
10.3.1 Timer Control Register (TCR).............................................................................. 250
10.3.2 Timer Mode Register (TMDR)............................................................................. 254
10.3.3 Timer I/O Control Register (TIOR)...................................................................... 257
10.3.4 Timer Compare Match Clear Register (TCNTCMPCLR).................................... 276
10.3.5 Timer Interrupt Enable Register (TIER)............................................................... 277
10.3.6 Timer Status Register (TSR)................................................................................. 282
10.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 290
10.3.8 Timer Input Capture Control Register (TICCR)................................................... 291
10.3.9 Timer Synchronous Clear Register (TSYCR) ...................................................... 293
10.3.10 Timer A/D Converter Start Request Control Register (TADCR) ......................... 295
10.3.11 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4)...................................................................... 298
10.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4) ................................................................ 298
10.3.13 Timer Counter (TCNT)......................................................................................... 299
10.3.14 Timer General Register (TGR) ............................................................................. 299
10.3.15 Timer Start Register (TSTR) ................................................................................ 300
10.3.16 Timer Synchronous Register (TSYR)................................................................... 302
10.3.17 Timer Counter Synchronous Start Register (TCSYSTR) ..................................... 304
Rev. 3.00 May 17, 2007 Page xiv of xliv
Share Link: 