PM4388 Просмотр технического описания (PDF) - PMC-Sierra

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PM4388

OCTAL T1 FRAMER

PMC-Sierra 

DATA SHEET

PMC-960840

ISSUE 5

PM4388 TOCTL

OCTAL T1 FRAMER

• Available in a 14 mm by 20 mm 128 pin Plastic Quad Flat Pack (PQFP) or an

11mm by 11mm 128 pin Chip Array Ball Grid Array (CABGA) package.

Each one of eight receiver sections:

• Accepts gapped data streams to support higher rate demultiplexing.

• Provides Red, Yellow, and AIS alarms integration.

• Provides programmable in-band loopback code detection.

• Indicates signaling state change, and 2 superframes of signaling debounce

on a per-DS0 basis.

• Provides an HDLC interface with 128 bytes of buffering for terminating the

facility data link.

• Provides performance monitoring counters sufficiently large as to allow

performance monitor counter polling at a minimum rate of once per second.

Optionally, updates the performance monitoring counters and interrupts the

microprocessor once per second, timed to the receive line.

• Provides an optional elastic store which may be used to time the ingress

streams to a common clock and frame alignment, or to facilitate per-DS0

loopbacks.

Each one of eight transmitter sections:

• May be timed to its associated receive clock (loop timing) or may derive its

timing from a common egress clock or a common transmit clock; the transmit

line clock may be synthesized from an N*8kHz reference.

• Provides minimum ones density through Bell (bit 7), GTE or “jammed bit 8”

zero code suppression on a per-DS0 basis.Provides a 128 byte buffer to allow

insertion of the facility data link using the host interface.

• Supports transmission of the alarm indication signal (AIS) or the Yellow alarm

signal in both SF and ESF formats.

• Provides a digital phase locked loop for generation of a low jitter transmit

clock.

• Provides a FIFO buffer for jitter attenuation and rate conversion in the

transmitter.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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