NIS5102(2006) Просмотр технического описания (PDF) - ON Semiconductor
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NIS5102 Datasheet PDF : 14 Pages
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NIS5102
High Side
SMART HotPlugE IC/Inrush
Limiter/Circuit Breaker
The NIS5102 is a controller/FET IC that saves design time and
reduces the number of components required for a complete hot swap
application. It is designed for +12 V applications.
This chip includes a time delay for sequencing applications. It has a
dual function OVLO pin that allows multiple units to be ganged
together for simultaneous turn−on and shutdown, allowing units to be
operated in parallel. It allows for user selectable undervoltage and
overvoltage lockout levels. Its unique current limit circuit allows for
adjustable current limit levels with no external power resistor. An
internal temperature limiting circuit greatly increases the reliability of
this device.
Features
• Integrated Power Device
• Power Device Thermally Protected
• No External Current Shunt Required
• Simultaneous Shutdown and Startup for Parallel Operation
• Enable/Timer Pin
• Power Good
• 9.0 to 18 V Input Range
• 10 mW
• Main/Mirror MOSFET Current Ratio 1000:1
• Pb−Free Packages are Available
Typical Applications
• High Availability Systems
• Electronic Circuit Breaker
• 12 V Distributed Architecture
http://onsemi.com
ÎÎÎÎ
MARKING
DIAGRAM
1
5102QPxH
AWLYWWG
9x9 MM, 12 PIN PLLP
CASE 488AB
x
= 1 or 2
A
= Assembly Location
WL = Wafer Lot
Y
= Year
WW = Work Week
G
= Pb−Free
PIN CONNECTIONS
12
1
11
2
10
13
3
9
4
8
5
7
6
(Bottom View)
ORDERING INFORMATION
Device
Package
Shipping†
NIS5102QP1HT1 9x9 mm 1500/Tape & Reel
(Latchoff)
12 Pin PLLP
NIS5102QP1HT1G 12 Pin PLLP 1500/Tape & Reel
(Latchoff)
(Pb−Free)
NIS5102QP2HT1 9x9 mm 1500/Tape & Reel
(Auto−Retry)
12 Pin PLLP
NIS5102QP2HT1G 12 Pin PLLP 1500/Tape & Reel
(Auto−Retry)
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
1
October, 2006 − Rev. 5
Publication Order Number:
NIS5102/D
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