NIS5102(2006) Просмотр технического описания (PDF) - ON Semiconductor

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NIS5102
(Rev.:2006)

High Side SMART HotPlug IC/Inrush Limiter/Circuit Breaker

ON Semiconductor 

NIS5102

OPERATING DESCRIPTION

Operation

The NIS5102 has a variety of shutdown and protection

features that make this part extremely versatile as well as

rugged. For the unit to operate, the input voltage must be

within the operating range of the part which is set by the

UVLO and OVLO bias resistors. The enable must also be

high for operation. Current and thermal limit circuits

constantly monitor the operation and will protect the unit if

either of these parameters exceeds its preset limit.

An additional shutdown method, is the use of the OVLO

pin, which can be tied in parallel. This allows multiple units

to be either operated in parallel, and will shutdown and turn

on simultaneously for any fault other than an overvoltage, or

it allows these hot plug devices to control independent loads,

and shutdown and turn on simultaneously.

Faults

Once the load capacitance is charged, the SENSEFETt

will become fully enhanced as long as the current does not

reach the current limit threshold, or is shutdown due to an

overvoltage, undervoltage or thermal fault. Both the UVLO

and OVLO circuits incorporate hysteresis to assure clean

turn−on and turn−offs with no chatter. The thermal latching

circuit will require the input power to be recycled to resume

operation after a fault. The current limit is always active, so

any transient or overload will always be limited.

Circuit Description

Enable/Timer

The enable/timer pin can function either as a direct enable

pin, or as a time delay. In the enable mode, an open collector

device is connected to this pin. When the device is in its low

impedance mode, this pin is low and the operation of the chip

is disabled. If a time delay is required, a capacitor is added

to this pin. Figure 17 shows the equivalent circuit for the

enable.

Enable/

Timer

80 mA

+

2.2 V

−

Enabled

NIS5102

Figure 17. Enable/Timer Circuit

If a capacitor is added without an open collector device,

the turn on will be delayed from the time at which the UVLO

voltage is reached. If an open collector device is also used,

the delay will start from the time that it goes into its high

impedance state. The capacitor is charged by an internal

current source.

There is an inherent delay in the turn on of the hot plug

device, due to the method of gate drive used. The gate of the

power FET is charged through a high impedance resistor,

and from the time that the gate starts charging until the time

that it reaches its threshold voltage, there will be no

conduction. Once the gate reaches its threshold voltage, the

output current will begin a controlled ramp up phase.

This delay will be added to any timing delay due to the

enable/timer circuit.

Power Good

The power good circuit monitors the VGS voltage of the

power SENSEFET and compares it with the output voltage

of the internal charge pump. Once the VGS of the power

SENSEFET reaches around 90% of the internal charge

pump output voltage, the power good will change its state

from low impedance to high impedance but only after the

power good delay has elapsed. Figure 10 shows the power

good behavior during the startup of the NIS5102 device, an

external pullup resistor from power good to VCC was used.

The power good will change its state from high impedance

to low impedance in the event of any fault condition such as

short circuit and overvoltage.

Undervoltage Lockout

The UVLO circuit holds the chip off when the input

voltage is less than the turn−on limit. It includes internal

hysteresis to assure clean on/off switching. An internal

divider sets the turn−on voltage level at 16 V. This voltage

can be reduced by adding an external resistor from the

UVLO pin to the VCC pin. The equivalent circuit is shown

in Figure 18.

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