HI5728EVAL1(1999) Просмотр технического описания (PDF) - Intersil
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HI5728EVAL1 Datasheet PDF : 17 Pages
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HI5728
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
39-30
1-6, 48-46
8
15
23
22
14, 24
13, 18, 19, 25
17
16
20
21
QD9 (MSB) Through Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
QD0 (LSB)
channel.
ID9 (MSB) Through Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I chan-
ID0 (LSB)
nel.
SLEEP
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20µA active pull-down current.
REFLO
REFIO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable.
Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
enabled. Use 0.1µF cap to ground when internal reference is enabled.
FSADJ
ICOMP1, QCOMP1
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current Per Channel = 32 x IFSADJ.
Reduces noise. Connect each to AVDD with 0.1µF capacitor near each pin. The ICOMP1 and QCOMP1
pins MUST be tied together externally.
AGND
Analog Ground Connections.
IOUTB
The complimentary current output of the I channel. Bits set to all 0s gives full scale current.
IOUTA
Current output of the I channel. Bits set to all 1s gives full scale current.
QOUTB
The complimentary current output of the Q channel. Bits set to all 0s gives full scale current.
QOUTA
Current output of the Q channel. Bits set to all 1s gives full scale current.
11, 27
12, 26
10, 28, 41, 44
9, 29, 40, 45
43
42
NC
AVDD
DGND
DVDD
ICLK
QCLK
No Connect. Recommended: connect to ground.
Analog Supply (+2.7V to +5.5V).
Digital Ground.
Supply voltage for digital circuitry (+2.7V to +5.5V).
Clock input for I channel. Positive edge of clock latches data.
Clock input for Q channel. Positive edge of clock latches data.
4
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