HI5721-EVS(1999) Просмотр технического описания (PDF) - Intersil
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HI5721-EVS Datasheet PDF : 14 Pages
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HI5721
Absolute Maximum Ratings
Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AVEE to AGND, ARTN . . . . . -5.5V
Digital Input Voltages (D9-D0, CLK, INVERT) . . . . . . . VCC to -0.5 V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . .500µA
Control Amplifier Input Voltage Range. . . . . . . . . . . . AGND to -4.0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA
Reference Input Voltage Range . . . . . . . . . . . . . . . . . -3.7 V to AVEE
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Power Dissipation
θJA(oC/W)
55
70
HI5721BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .750mW
Maximum Junction Temperature
HI5721BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications ATAVE=E2,5DoVCEfEor=A-l4l .T9y4pitcoa-l5V.a4l6uVe,sVCC = +4.75 to +5.25V, CTRL AMP IN = REF OUT,
PARAMETER
TEST CONDITIONS
HI5721BI
TA = -40oC TO 85oC
MIN TYP MAX
UNITS
SYSTEM PERFORMANCE
Resolution
10
-
-
Bits
Integral Linearity Error, INL
(Note 4) (“Best Fit” Straight Line)
-
±0.5 ±1.5 LSB
Differential Linearity Error, DNL
(Note 4)
-
±0.5 ±1.0 LSB
Offset Error, IOS
Full Scale Gain Error, FSE
Offset Drift Coefficient
(Note 4)
(Notes 2, 4)
(Note 3)
-
16
75
µA
-
2
10
%
-
0.1
-
µA/oC
Full Scale Output Current, IFS
Output Voltage Compliance Range
(Note 3)
- -20.48 -
mA
-1.5
-
+3.0
V
DYNAMIC CHARACTERISTICS
Throughput Rate
(Note 3)
125.0 -
-
MSPS
Output Voltage Full Scale Step Settling Time, tSETT FS To ±0.5 LSB Error Band RL = 50Ω (Note 3)
-
4.5
-
ns
Output Voltage Small Step Settling Time, tSETT SM
100mV Step to ±0.5 LSB Error Band, RL = 50Ω
-
3.5
-
ns
(Note 3)
Singlet Glitch Area, GE (Peak Glitch)
Doublet Glitch Area, (Net Glitch)
RL = 50Ω (Note 3)
-
3.5
-
pV•s
-
1.5
-
pV•s
Output Slew Rate
RL = 50Ω, DAC Operating in Latched Mode
(Note 3)
- 1,000 -
V/µs
Output Rise Time
RL = 50Ω, DAC Operating in Latched Mode
(Note 3)
-
675
-
ps
Output Fall Time
RL = 50Ω, DAC Operating in Latched Mode
(Note 3)
-
470
-
ps
3-36
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