MT9074 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT9074

T1/E1/J1 Single Chip Transceiver

Zarlink Semiconductor Inc 

MT9074

Data Sheet

• Data link pins TxDL, RxDL, RxDLCLK and TxDLCLK;

• HDLC Controller with a 128 byte FIFO.

A second HDLC Controller with a 128 byte FIFO is available for connection to timeslot 16 in E1 mode.

Functional Description

MT9074 Line Interface Unit (LIU)

Receiver

The receiver portion of the MT9074 LIU consists of an input signal peak detector, an optional equalizer with two

separate high pass sections, a smoothing filter, data and clock slicers and a clock extractor. Receive equalization

gain can be set manually (i.e., software) or it can be determined automatically by peak detectors.

The output of the receive equalizer is conditioned by a smoothing filter and is passed on to the clock and data slicer.

The clock slicer output signal drives a phase locked loop, which generates an extracted clock (C1.50). This

extracted clock is used to sample the output of the data comparator.

In T1 mode, the receiver portion of the LIU can reliably recover clock and data from signals attenuated by up to

30 dB @ 772 kHz (translates to 5000 ft. of PIC 24 AWG cable) and tolerate jitter to the maximum specified by AT&T

TR 62411 (see Figure 3).

In E1 mode the receiver portion of the LIU can reliably recover clock and data from signals attenuated by up to

30 dB @ 1024 kHz (translates to 1900 m. of PIC 0.65 mm or 22 AWG cable) and tolerate jitter to the maximum

specified by ETS 300 011 (Figure 4).

The LOS output pin function is user selectable to indicate any combination of loss of signal and/or loss of basic

frame synchronization condition.

The LLOS (Loss of Signal) status bit indicates when the receive signal level is lower than the analog threshold for at

least 1 millisecond, or when more than 192 consecutive zeros have been received. In E1 mode the analog

threshold is either of -20 dB or -40 dB. For T1 mode the analog threshold is -40 dB.

In T1 mode, the receive LIU circuit requires a terminating resistor of 100 Ω across the device side of the receive 1:1

transformer.

In E1 mode the receive LIU circuit requires a terminating resistor of either 120 Ω or 75 Ω across the device side of

the receive1:1 transformer.

The jitter tolerance of the clock extractor circuit exceeds the requirements of TR 62411 in T1 mode (see Figure 3)

and G.823 in E1 mode (see Figure 4).

Transmitter

The transmit portion of the MT9074 LIU consists of a high speed digital-to-analog converter and complementary

line drivers.

When a pulse is to be transmitted, a sequence of digital values (dependent on transmit equalization) are read out of

a ROM by a high speed clock. These values drive the digital-to-analog converter to produce an analog signal,

which is passed to the complementary line drivers.

The complementary line drivers are designed to drive a 1:2 step-up transformer (see Figure 5 for T1 mode and

Figure 6 for E1 mode). A 0.47 uF capacitor is required between the TTIP and the transmit transformer. Resistors

RT (as shown in Figure 5) are for termination for transmit return loss. The values of RT may be optimized for T1

mode, E1 120 Ω lines, E1 75 Ω lines or set at a compromise value to serve multiple applications. Program the LIU

Control Word (address 1FH page 1) to adjust the pulse amplitude accordingly.

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Zarlink Semiconductor Inc.

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