MT9074 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT9074 Datasheet PDF : 151 Pages
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MT9074
Data Sheet
Pin Description
Pin #
68 Pin 100 Pin
PLCC MQFP
Name
Description
13 - 86-89
16
D0 - D3
Data 0 to Data 3 (Three-state I/O). These signals combined with D4-D7 form the
bidirectional data bus of the microprocessor interface (D0 is the least significant
bit).
17
90
Vss Negative Power Supply (Input). Digital ground.
18
91
IC
Internal Connection. Tie to Vss (ground) for normal operation.
19
92
INT/MOT Intel/Motorola Mode Selection (Input).A high on this pin configures the
processor interface for the Intel parallel non-multiplexed bus type. A low configures
the processor interface for the Motorola parallel non-multiplexed type.
20
93
VDD Positive Power Supply (Input). Digital supply (+5 V± 5%).
21 - 94-97
24
D4 - D7
Data 4 to Data 7 (Three-state I/O). These signals combined with D0-D3 form the
bidirectional data bus of the parallel processor interface (D7 is the most significant
bit).
25
98
R/W/WR Read/Write/Write Strobe (Input). In Motorola mode (R/W), this input controls the
direction of the data bus D[0:7] during a microprocessor access. When R/W is
high, the parallel processor is reading data from the MT9074. When low, the
parallel processor is writing data to the MT9074. For Intel mode (WR), this active
low write strobe configures the data bus lines as input.
26 - 99, 8-11 AC0 - AC4 Address/Control 0 to 4 (Inputs). Address and control inputs for the
30
non-multiplexed parallel processor interface. AC0 is the least significant input.
31
12
GNDARx Receive Analog Ground (Input). Analog ground for the LIU receiver.
32
13
33
14
RTIP
RRING
Receive TIP and RING (Input). Differential inputs for the receive line signal - must
be transformer coupled (See Figure 5). In digital framer mode these are TTL level
inputs that connect to the digital outputs of a receiver. If the receiver serial data
output is NRZ connect that output to RTIP. If the receiver data output is split phase
unipolar signal connect one signal to RTIP and the complementary signal to
RRING.
34
15
VDDARx Receive Analog Power Supply (Input). Analog supply for the LIU receiver (+5 V
± 5%).
35
16
VDD Positive Power Supply (Input). Digital supply (+5 V ± 5%).
36
17
VSS Negative Power Supply (Input). Digital ground.
37
18
TxA Transmit A (Output). When the internal LIU is disabled (digital framer only
mode), if control bit NRZ=1, and NRZ output data is clocked out on pin TxA with
the rising edge of C1.50 (TxB has no function when NRZ format is selected). If
NRZ=0, pins TxA and TxB are a complementary pair of signals that output digital
dual-rail clocked out with the rising edge of C1.50.
38
19
TxB Transmit B (Output). When the internal LIU is disabled and control bit NRZ=0,
pins TxA and TxB are a complementary pair of signals that output digital dual-rail
data clocked out with the rising edge of C1.50.
39
20 RxDLCLK Data Link Clock (Output). A gapped clock signal derived from the extracted clock
from the line clock, available for an external device to clock in RxDL data (at 4, 8,
12, 16 or 20 kHz) on the rising edge.
13
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