MT9076B Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

Номер в каталоге

Компоненты Описание

производитель

MT9076B

T1/E1/J1 3.3 V Single Chip Transceiver

Zarlink Semiconductor Inc 

MT9076B

Data Sheet

Note:

ADDRESS

00111000

00111010

00000001

CONTROL

00000011

ONE SECOND REPORT

G1 = 1

G2 =1

G3 =1

G4 =1

G5 =1

G6 =1

SE=1

FE-=1

LV=1

SL=1

LB=1

U1,U2=0

R=0

NmNI=00,01,10,11

FCS

VARIABLE

INTERPRETATION

SAPI = 14, C/R = 0 (CI) EA = 0

SAPI = 14, C/R = 1(Carrier) EA = 0

TEI = 0, EA =1

INTERPRETATION

Unacknowledged Information Transfer

INTERPRETATION

CRC Error Event =1

1 < CRC Error Event < 5

5 < CRC Error Event < 10

10 < CRC Error Event < 100

100 < CRC Error Event < 319

CRC Error Event > 320

Severely - Errored Framing Event >=1

Frame Synchronization Bit Error Event >=1

Line code Violation Event >=1

Slip Event >=1

Payload Loopback Activated

Under Study for sync.

Reserved - set to 0

One Second Module 4 counter

INTERPRETATION

CRC16 Frame Check Sequence

7.2.1 External Data Link

In T1 mode, MT9076 has two pairs of pins (TxDL and TxDLCLK, RxDL and RxDLCLK) dedicated to transmitting

and receiving bits in the selected overhead bit positions. Pins TxDLCLK and RxDLCLK are clock outputs available

for clocking data into the MT9076 (for transmit) or external device (for receive information). Each clock operates at

4 Khz. In the SLC-96 mode the optional serial data link is multiplexed into the Fs bit position. In the ESF mode, the

serial data link is multiplexed into odd frames, i.e., the FDL bit positions.

7.2.2 Bit - Oriented Messaging

In T1 mode, MT9076 Bit oriented messaging may be selected by setting bit 6 (BIOMEn) in the Data Link Control

Word (page 1H, address 12H). The transmit data link will contain the repeating serial data stream

111111110xxxxxx0 where the byte 0xxxxxx0 originates from the user programmed register “Transmit Bit Oriented

Message” - page 1H address 13H. The receive BIOM register “Receive Bit Oriented Message” - page 3H, address

15H, will contain the last received valid message (the 0xxxxxx0 portion of the incoming serial bit stream). To

prevent spurious inputs from creating false messages, a new message must be present in 7 of the last 10

appropriate byte positions before being loaded into the receive BIOM register. When a new message has been

received, a maskable interrupt (maskable by setting bit 1 low in Interrupt Mask Word Three - page 1H, address

1EH) may occur.

8.0 Floating HDLC Channels

MT9076 has three embedded HDLC controllers (HDLC0, HDLC1, HDLC2) each of which includes the following

features:

• Independent transmit and receive FIFO's;

• Receive FIFO maskable interrupts for nearly full (programmable interrupt levels) and overflow conditions;

• Transmit FIFO maskable interrupts for nearly empty (programmable interrupt levels) and underflow

conditions;

• Maskable interrupts for transmit end-of-packet and receive end-of-packet;

40

Zarlink Semiconductor Inc.

Share Link: