MT9076B Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT9076B

T1/E1/J1 3.3 V Single Chip Transceiver

Zarlink Semiconductor Inc 

MT9076B

Data Sheet

• Maskable interrupts for receive bad-frame (includes frame abort);

• Transmit end-of-packet and frame-abort functions.

Each controller may be attached to any of the active 64 Kkb/s channels (24 in the case of T1, 31 in the case of E1).

HDLC0 may also be attached to the FDL in a T1 ESF link by connecting it to phantom channel 31 when

programming the HDLC Select Word. If HDLC0 is attached to channel 0 in E1 mode, only the activated Sa bits (as

per the Multiframe and Data Selection Word) will be transmit and received by the controller.

8.1 Channel Assignment

In T1 mode, any DS1 channel can be connected to either of HDLC0,1 or 2, operating at 56 or 64 Kb/s. Setting

control bit H1R64 (address 12 H on page 01H) high selects 64 Kb/s operation for all HDLCs. Setting this bit low

selects 56 Kb/s for all HDLC. Interrupts from any of the HDLCs are masked when they are disconnected.

In E1 mode, all PCM-30 channels except channel 0 can be connected to either of HDLC0,1 or 2. HDLC1 and

HDLC2 operate at 64 Kb/s. HDLC0 operates at 64 kb/s when connected to any of channels 1 to 31. When

connected to channel 0 HDLC0 operates at 4, 8, 12, 16 or 20 Kb/s depending on the number of activated Sa bits.

HDLCs can be activated by programming the HDLC Select Words (page 02H, addresses 19H, 1AH and 1BH for

HDLC0, HDLC1 and HDLC2 respectively).

8.2 HDLC Description

The HDLC handles the bit oriented packetized data transmission as per X.25 level two protocol defined by CCITT. It

provides flag and abort sequence generation and detection, zero insertion and deletion, and Frame Check

Sequence (FCS) generation and detection. A single byte, dual byte and all call address in the received frame can

be recognized. Access to the receive FCS and inhibiting of transmit FCS for terminal adaptation are also provided.

Each HDLC controller has a 128 byte deep FIFO associated with it. The status and interrupt flags are

programmable for FIFO depths that can vary from 16 to 128 bytes in steps of 16 bytes. These and other features

are enabled through the HDLC control registers on page 0BH and 0CH.

8.2.1 HDLC Frame Structure

In T1 mode or E1 mode, a valid HDLC frame begins with an opening flag, contains at least 16 bits of address and

control or information, and ends with a 16 bit FCS followed by a closing flag. Data formatted in this manner is also

referred to as a “packet”. Refer to Table 17: HDLC Frame Format

Flag (7E)

Data Field

FCS

Flag (7E)

One Byte

01111110

n Bytes

n≥2

Two Bytes

One Byte

01111110

Table 17 - HDLC Frame Format

All HDLC frames start and end with a unique flag sequence “01111110”. The transmitter generates these flags and

appends them to the packet to be transmitted. The receiver searches the incoming data stream for the flags on a

bit- by-bit basis to establish frame synchronization.

The data field consists of an address field, control field and information field. The address field consists of one or

two bytes directly following the opening flag. The control field consists of one byte directly following the address

field. The information field immediately follows the control field and consists of N bytes of data. The HDLC does not

distinguish between the control and information fields and a packet does not need to contain an information field to

be valid.

The FCS field, which precedes the closing flag, consists of two bytes. A cyclic redundancy check utilizing the

CRC-CCITT standard generator polynomial “X16+X12+X5+1” produces the 16-bit FCS. In the transmitter the FCS is

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Zarlink Semiconductor Inc.

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