MT9076B Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
Номер в каталоге
Компоненты Описание
производитель
MT9076B Datasheet PDF : 172 Pages
| |||
MT9076B
Data Sheet
The RxDLCLK signal (pin 39 - PLCC, pin 14 - LQFP) is derived from the receive extracted clock and is aligned with
the receive data link output RxDL. The HDB3 decoded receive data, at 2.048 Mbit/s, is clocked out of the device on
pin RxDL (pin 40 in PLCC, pin 15 in LQFP). In order to facilitate the attachment of this data stream to a Data Link
controller, the clock signal RxDLCLK consists of positive pulses, of nominal width of 244 ns, during the Sa bit cell
times that are selected for the data link.This selection is made by programming address 17H of master control page
01H. No DL data will be lost or repeated when a receive frame slip occurs. See AC Electrical Characteristics for
timing requirements.
7.2 Data Link Operation in T1 Mode
SLC-96 and ESF protocol allow for carrier messages to be embedded in the overhead bit position. The MT9076
provides 3 separate means of controlling these data links. See Data Link Control Word - address 12H, page 1H.
• The data links (transmit and receive) may be sourced (sunk) from an external controller using dedicated pins
on the MT9076 in T1 mode (enabled by setting the bit 7 - EDL of the Data link Control Word).
• Bit Oriented Messages may be transmit and received via a dedicated TxBOM register (page 1H, address
13H) and a RxBOM (page 3H, address 15H). Transmission is enabled by setting bit 6 - BIOMEn in the Data
link Control Word. Bit - oriented messages may be periodically interrupted (up to once per second) for a
duration of up to 100 milliseconds. This is to accommodate bursts of message - oriented protocols. See
Table 16 for message structure.
Octet #
8
7
6
5
4
3
2
1
Content
1
F
L
A
G
01111110
2
S
A
P
I
C/R
EA 00111000 or
00111010
3
T
E
I
EA
00000001
4
C
O
N
T
R
O
L
00000011
5
G3
LV
G4
U1
U2
G5
SL
G6
t0
6
FE
SE
LB
G1
R
G2
Nm
NI
t0
7
G3
LV
G4
U1
U2
G5
SL
G6
t0-1
8
FE
SE
LB
G1
R
G2
Nm
NI
t0-1
9
G3
LV
G4
U1
U2
G5
SL
G6
t0-2
10
FE
SE
LB
G1
R
G2
Nm
NI
t0-2
11
G3
LV
G4
U1
U2
G5
SL
G6
t0-3
12
FE
SE
LB
G1
R
G2
Nm
NI
t0-3
13
F
C
S
VARIABLE
14
Table 16 - Message Oriented Performance Report Structure (T1.403 and T1.408)
39
Zarlink Semiconductor Inc.
Share Link: 