MT9074 Просмотр технического описания (PDF) - Mitel Networks

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MT9074

T1/E1/J1 Single Chip Transceiver

Mitel Networks 

MT9074

Advance Information

channels from the write pointer, a slip will occur,

which will put the read pointer 28 channels from the

write pointer. This provides a worst case hysteresis

of 13 channels peak (26 channels peak-to-peak) or a

wander tolerance of 208 UI.

Framing Algorithm

Frame Alignment in T1 Mode

In T1 mode MT9074 will synchronize to DS1 lines

formatted with either the D4 or ESF protocol. In

either mode the framer maintains a running 3 bit

history of received data for each of the candidate bit

positions. Candidate bit positions whose incoming

patterns fail to match the predicted pattern (based on

the 3 bit history) are winnowed out. If, after a 10 bit

history has been examined, only one candidate bit

position remains within the framing bit period, the

receive side timebase is forced to align to that bit

position. If no candidates remain after a 10 bit

history, the process is re-initiated. If multiple

candidates exist after a 24 bit history timeout period,

the framer forces the receive side timebase to

synchronize to the next incoming valid candidate bit

position. In the event of a reframe, the framer starts

searching at the next bit position over. This prevents

persistent locking to a mimic as the controller may

initiate a software controlled reframe in the event of

locking to a mimic.

Under software control the framing criteria may be

tuned (see Framing Mode Select Register, page 1H,

address 10H). Selecting D4 framing invites a further

decision whether or not to include a cross check of

Fs bits along with the Ft bits. If Fs bits are checked

(by setting control bit CXC high - bit 5 of the Framing

Mode Select Word, page 1H, address 10H),

multiframer alignment is forced at the same time as

terminal frame alignment. If only Ft bits are checked,

multiframe alignment is forced separately, upon

detection of the Fs bit history of 00111 (for normal

D4 trunks) or 000111000111 (for SLC-96 trunks).

For D4 trunks, a reframe on the multiframe alignment

may be forced at any time without affecting terminal

frame alignment.

In ESF mode the circuit will optionally confirm the

CRC-6 bits before forcing a new frame alignment.

This is programmed by setting control bit CXC high

(bit 5 of the Framing Mode Select Word, page 1H,

address 10H). A CRC-6 confirmation adds a

minimum of 6 milliseconds to the reframe time. If no

CRC-6 match is found after 16 attempts, the framer

moves to the next valid candidate bit position

(assuming other bit positions contain a match to the

framing pattern) or re-initiates the whole framing

procedure (assuming no bit positions have been

found to match the framing pattern).

The framing circuit is off - line. During a reframe, the

rest of the circuit operates synchronous with the last

frame alignment. Until such time as a new frame

alignment is achieved, the signalling bits are frozen

in their states at the time that frame alignment was

lost, and error counting for Ft, Fs, ESF framing

pattern or CRC-6 bits is suspended.

Frame Alignment in E1 mode

In E1 mode MT9074 contains three distinct framing

algorithms: basic frame alignment, signalling

multiframe alignment and CRC-4 multiframe

alignment. Figure 17 is a state diagram that

illustrates these algorithms and how they interact.

Read Pointer Write Pointer Read Pointer

60 CH

2 CH

47 CH

512 Bit

Elastic

Store

15 CH

13 CH

Wander Tolerance

34 CH

Read Pointer

30

28 CH

Read Pointer

-13 CH

Figure 14 - Read and Write Pointers in the Slip Buffers

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