MT9074 Просмотр технического описания (PDF) - Mitel Networks

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MT9074

T1/E1/J1 Single Chip Transceiver

Mitel Networks 

MT9074

Advance Information

flag followed by the data and closing flag is sent and

zero insertion still included, but no CRC. That is, the

FCS is injected by the microprocessor as part of the

data field. This is used in V.120 terminal adaptation

for synchronous protocol sensitive UI frames.

HDLC Receiver

After initialization and enabling, the receiver clocks in

serial data, continuously checking for Go-aheads (0

1111 1110), flags (0111 1110), and Idle Channel

states (at least fifteen ones). When a flag is

detected, the receiver synchronizes itself to the

serial stream of data bits, automatically calculating

the FCS. If the data length between flags after zero

removal is less than 25 bits, then the packet is

ignored so no bytes are loaded into Rx FIFO. When

the data length after zero removal is between 25 and

31 bits, a first byte and bad FCS code are loaded into

the Rx FIFO (see definition of RQ8 and RQ9 below).

For an error-free packet, the result in the CRC

register should match the HEX pattern of ’F0B8’

when a closing flag is detected.

If address recognition is required, the Receiver

Address Recognition Registers are loaded with the

desired address and the Adrec bit in the Control

Register 1 is set high. Bit 0 of the Address Registers

is used as an enable bit for that byte, thus allowing

either or both of the first two bytes to be compared to

the expected values. Bit 0 of the first byte of the

address received (address extension bit) will be

monitored to determine if a single or dual byte

address is being received. If this bit is 0 then a two

byte address is being received and then only the first

six bits of the first address byte are compared. An all

call condition is also monitored for the second

address byte; and if received the first address byte is

ignored (not compared with mask byte). If the

address extension bit is a 1 then a single byte

address is being received. In this case, an all call

condition is monitored for in the first byte as well as

the mask byte written to the comparison register and

the second byte is ignored. Seven bits of address

comparison can be realized on the first byte if this is

a single byte address by setting the Seven bit of

Control Register 2.

The following two Status Register bits (RQ8 and

RQ9) are appended to each data byte as it is written

to the Rx FIFO. They indicate that a good packet has

been received (good FCS and no frame abort), or a

bad packet with either incorrect FCS or frame abort.

The Status and Interrupt Registers should be read

before reading the Rx FIFO since status and

interrupt information correspond to the byte at the

output of the FIFO (i.e. the byte about to be read).

The Status Register bits are encoded as follows:

RQ9

1

0

1

0

RQ8

1

1

0

0

Byte status

last byte (bad packet)

first byte

last byte (good packet)

packet byte

The end-of-packet-detect (EOPD) interrupt indicates

that the last byte written to the Rx FIFO was an EOP

byte (last byte in a packet). The end-of-packet-read

(EopR) interrupt indicates that the byte about to be

read from the Rx FIFO is an EOP byte (last byte in a

packet). The Status Register should be read to see if

the packet is good or bad before the byte is read.

A minimum size packet has an 8-bit address, an 8-bit

control byte, and a 16-bit FCS pattern between the

opening and closing flags (see Section 9.3.2). Thus,

the absence of a data transmission error and a frame

length of at least 32 bits results in the receiver

writing a valid packet code with the EOP byte into Rx

FIFO. The last 16 bits before the closing flag are

regarded as the FCS pattern and will not be

transferred to the receiver FIFO. Only data bytes

(Address, Control, Information) are loaded into the

Rx FIFO.

In the case of an Rx FIFO overflow, no clocking

occurs until a new opening flag is received. In other

words, the remainder of the packet is not clocked into

the FIFO. Also, the top byte of the FIFO will not be

written over. If the FIFO is read before the reception

of the next packet then reception of that packet will

occur. If two beginning of packet conditions

(RQ9=0;RQ8=1) are seen in the FIFO, without an

intermediate EOP status, then overflow occurred for

the first packet.

The receiver may be enabled independently of the

transmitter. This is done by setting the RXEN bit of

Control Register 1. Enabling happens immediately

upon writing to the register. Disabling using RXEN

will occur after the present packet has been

completely loaded into the FIFO. Disabling can occur

during a packet if no bytes have been written to the

FIFO yet. Disabling will consist of disabling the

internal receive clock. The FIFO, Status, and

Interrupt Registers may still be read while the

receiver is disabled. Note that the receiver requires a

flag before processing a frame, thus if the receiver is

enabled in the middle of an incoming packet it will

ignore that packet and wait for the next complete

one.

The receive CRC can be monitored in the Rx CRC

Registers. These registers contain the actual CRC

sent by the other transmitter in its original form; that

is, MSB first and bits inverted. These registers are

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