MT9074 Просмотр технического описания (PDF) - Mitel Networks

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MT9074

T1/E1/J1 Single Chip Transceiver

Mitel Networks 

Advance Information

MT9074

messages, a new message must be present in 7 of

the last 10 appropriate byte positions before being

loaded into the receive BIOM register. When a new

message has been received, a maskable interrupt

(maskable by setting bit 1 low in Interrupt Mask Word

Three - page 1H, address 1EH) may occur.

Dual HDLC

mode. It should be noted that the AIS16S function

will always be active and the TAIS16 (page 01H,

address 11h) function will override all other transmit

signalling.

HDLC1 can be selected by setting the control bit

HDLC1. When this bit is zero all interrupts from

HDLC1 are masked.

MT9074 has two embedded HDLC controllers

(HDLC0, HDLC1) each of which includes the

following features:

• Independent transmit and receive FIFO's;

• Receive FIFO maskable interrupts for nearly

full (programmable interrupt levels) and

overflow conditions;

• Transmit FIFO maskable interrupts for

nearly empty (programmable

interrupt

levels) and underflow conditions;

• Maskable interrupts for transmit end-of-

packet and receive end-of-packet;

• Maskable interrupts for receive bad-frame

(includes frame abort);

• Transmit end-of-packet and frame-abort

functions.

HLDC0 Functions

In T1 mode ESF Data Link (DL) can be connected to

internal HDLC0, operating at a bit rate of 4 kbits/sec.

HDLC0 can be activated by setting the control bit 5,

address 12H in Master Control Page 0. Interrupts

from HDLC0 are masked when it is disconnected.

In E1 mode when connected to the Data Link (DL)

HDLC0 will operate at a selected bit rate of 4, 8, 12,

16 or 20 kbits/sec. HDLC0 can be selected by setting

the control bit HDLC0 (page 01H, address 12H).

When this bit is zero all interrupts from HDLC0 are

masked. For more information refer to following

sections.

HDLC Description

The HDLC handles the bit oriented packetized data

transmission as per X.25 level two protocol defined

by ITU-T. It provides flag and abort sequence

generation and detection, zero insertion and

deletion, and Frame Check Sequence (FCS)

generation and detection. A single byte, dual byte

and all call address in the received frame can be

recognized. Access to the receive FCS and inhibiting

of transmit FCS for terminal adaptation are also

provided. Each HDLC controller has a 128 byte deep

FIFO associated with it. The status and interrupt

flags are programmable for FIFO depths that can

vary from 16 to 128 bytes in steps of 16 bytes. These

and other features are enabled through the HDLC

control registers on page 0BH and 0CH.

HDLC Frame structure

In T1 mode or E1 mode a valid HDLC frame begins

with an opening flag, contains at least 16 bits of

address and control or information, and ends with a

16 bit FCS followed by a closing flag. Data formatted

in this manner is also referred to as a “packet”. Refer

to Table 17: HDLC Frame Format

Flag (7E) Data Field FCS Flag (7E)

One Byte

01111110

n Bytes

n≥2

Two One Byte

Bytes 01111110

Table 17 - HDLC Frame Format

HDLC1 Functions

In T1 mode DS1 channel 24 can be connected to

HDLC1, operating at 56 or 64 Kb/s. HDLC1 can be

activated by setting the control bit HDLC1 (page

01H, address 12H). Setting control bit H1R64

(address 12 H on page 01H) high selects 64 Kb/s

operation for HDLC1. Setting this bit low selects 56

Kb/s for HDLC1. Interrupts from HDLC1 are masked

when it is disconnected.

In E1 mode this controller may be connected to time

slot 16 under Common Channel Signalling (CCS)

All HDLC frames start and end with a unique flag

sequence “01111110”. The transmitter generates

these flags and appends them to the packet to be

transmitted. The receiver searches the incoming

data stream for the flags on a bit- by-bit basis to

establish frame synchronization.

The data field consists of an address field, control

field and information field. The address field consists

of one or two bytes directly following the opening

flag. The control field consists of one byte directly

following the address field. The information field

immediately follows the control field and consists of

23

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