ML674001 Просмотр технического описания (PDF) - Oki Electric Industry

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ML674001

32-bit ARM-Based General-Purpose Microcontroller

Oki Electric Industry 

OKI Semiconductor

FEDL674001-01

ML674001/67Q4002/67Q4003

External memory controller

Controls access of externally connected devices such as ROM (FLASH), SRAM, SDRAM (EDO DRAM), IO

devices, and internal FLASH memory.

(1) ROM (FLASH) access function : 1 bank

Supports 16-bit devices.

Supports FLASH memory: Byte write (can be written only by IF equivalent to SRAM).

In ML67Q4002/ML67Q4003, control internal FLASH access.

Configurable access timing.

(2) SRAM access function

: 1 bank

Supports 16-bit devices.

Supports asynchronous SRAM

Configurable access timing.

(3) DRAM access function

: 1 bank

Supports 16-bit device

Supports EDO/SDRAM

: Simultaneous connections to EDO-DRAM and SDRAM cannot be

made.

Configurable access timing.

(4) External IO access function

: 2 banks

Supports 8-bit/16-bit access

: Independent configuration for each bank

Each bank has two chip selects : XIOCS_N[3:0]

Supports external wait input

: XWAIT

Access Timing configurable for each bank independently

Power Management

HALT, STANDBY, clock gear, clock control functions are supported as power save functions.

(1) HALT mode

HALT object

CPU, internal RAM, AHB bus control

HALT mode setting: Set by the system control register.

Exit HALT mode due to: Reset, interrupt

(2) STANDBY mode

Stops the clock of entire LSI.

STANDBY mode setting: Specified by the system control register.

Exit STANDBY mode due to: Reset, external interrupt (other than EFIQ_N)

(3) Clock gear

This LSI has two clock systems, HCLK and CCLK. Configure HCLK and CCLK frequency.

HCLK: CPU, bus control, synchronous serial interface, I2C.

CCLK: Timers, PWM, UART, AD converter, etc.

(4) Clock control by each function unit

AD converter, PWM, Timers, DRAMC, DMAC, UART(FIFO), UART, Synchronous SIO, I2C.

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