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ML674001 Просмотр технического описания (PDF) - Oki Electric Industry

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ML674001 Datasheet PDF : 24 Pages
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OKI Semiconductor
FEDL674001-01
ML674001/67Q4002/67Q4003
Pin Name
I/O
Description
DMA control signals
DREQ[0]
DREQCLR[0]
TCOUT[0]
DREQ[1]
DREQCLR[1]
TCOUT[1]
UART
SIN
SOUT
CTS
DSR
DCD
DTR
RTS
RI
I Ch 0 DMA request signal, used when DMA controller configured for
DREQ type
O Ch 0 DREQ signal clear request. The DMA device responds to this
output by negating DREQ.
O Indicates to Ch 0 DMA device that last transfer has started.
I Ch 1 DMA request signal, used when DMA controller configured for
DREQ type
O Ch 1 DREQ signal clear request. The DMA device responds to this
output by negating DREQ.
O Indicates to Ch 1 DMA device that last transfer has started
I SIO receive signal
O SIO transmit signal
I Clear To Send.
Indicates that modem or data set is ready to transfer data. Bit 4 in
modem status register reflects this input.
I Data Set Ready.
Indicates that modem or data set is ready to establish a
communications link with UART.
Bit 5 in modem status register reflects this input.
I Data Carrier Detect.
Indicates that modem or data set has detected data carrier signal. Bit
7 in modem status register reflects this input.
Data Carrier Detect
O Data Terminal Ready.
Indicates that UART is ready to establish a communications link with
modem or data set. Bit 0 in modem control register controls this
output.
O Request To Send.
Indicates that UART is ready to transfer data to modem or data set. Bit
1 in modem control register controls this output.
I Ring Indicator. Indicates that modem or data set has received
telephone ring indicator. Bit 6 in modem status register reflects this
input.
Primary /
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Logic
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Negative
Negative
Negative
Negative
Negative
Negative
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