M68HC11ERG Просмотр технического описания (PDF) - Motorola => Freescale
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M68HC11ERG Datasheet PDF : 60 Pages
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M68HC11ERG/AD
Instruction Set
Instruction Set
Refer to Table 1, which shows all the M68HC11 instructions in all possible
addressing modes. For each instruction, the table shows the operand
construction, the number of machine code bytes, and execution time in
CPU E-clock cycles.
Table 1. Instruction Set (Sheet 1 of 8)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Condition Codes
Opcode Operand Cycles S X H I N Z V C
ABA
Add
A+B⇒A
INH
1B
—
2
—— ∆ — ∆ ∆ ∆ ∆
Accumulators
ABX
Add B to X
IX + (00 : B) ⇒ IX
INH
3A
—
3
————————
ABY
Add B to Y
IY + (00 : B) ⇒ IY
INH
18
3A
—
4
————————
ADCA (opr) Add with Carry
to A
A+M+C⇒A A
A
A
A
A
IMM
DIR
EXT
IND,X
IND,Y 18
89 ii
99 dd
B9 hh ll
A9 ff
A9 ff
2
—— ∆ — ∆ ∆ ∆ ∆
3
4
4
5
ADCB (opr) Add with Carry
to B
B+M+C⇒B B
B
B
B
B
IMM
DIR
EXT
IND,X
IND,Y 18
C9 ii
D9 dd
F9 hh ll
E9 ff
E9 ff
2
—— ∆ — ∆ ∆ ∆ ∆
3
4
4
5
ADDA (opr) Add Memory to
A
A+M⇒A
A
IMM
8B ii
A
DIR
9B dd
A
EXT
BB hh ll
A
IND,X
AB ff
A
IND,Y 18
AB ff
2
—— ∆ — ∆ ∆ ∆ ∆
3
4
4
5
ADDB (opr) Add Memory to
B
B+M⇒B
B
IMM
CB ii
B
DIR
DB dd
B
EXT
FB hh ll
B
IND,X
EB ff
B
IND,Y 18
EB ff
2
—— ∆ — ∆ ∆ ∆ ∆
3
4
4
5
ADDD (opr) Add 16-Bit to D D + (M : M + 1) ⇒ D
IMM
DIR
EXT
IND,X
IND,Y 18
C3 jj kk
D3 dd
F3 hh ll
E3 ff
E3 ff
4
———— ∆ ∆ ∆ ∆
5
6
6
7
ANDA (opr)
AND A with
Memory
A•M⇒A
A
IMM
84 ii
A
DIR
94 dd
A
EXT
B4 hh ll
A
IND,X
A4 ff
A
IND,Y 18
A4 ff
2
———— ∆ ∆ 0 —
3
4
4
5
ANDB (opr)
AND B with
Memory
B•M⇒B
B
IMM
C4 ii
B
DIR
D4 dd
B
EXT
F4 hh ll
B
IND,X
E4 ff
B
IND,Y 18
E4 ff
2
———— ∆ ∆ 0 —
3
4
4
5
ASL (opr) Arithmetic Shift
Left
0
C b7
b0
EXT
IND,X
IND,Y 18
78 hh ll
68 ff
68 ff
6
———— ∆ ∆ ∆ ∆
6
7
ASLA
Arithmetic Shift
A
INH
Left A
C b7
0
b0
48
—
2
———— ∆ ∆ ∆ ∆
ASLB
Arithmetic Shift
B
INH
Left B
C b7
0
b0
58
—
2
———— ∆ ∆ ∆ ∆
ASLD
Arithmetic Shift
INH
Left D
0
C b7 A b0 b7 B b0
05
—
3
———— ∆ ∆ ∆ ∆
MOTOROLA
M68HC11E Series Programming Reference Guide
13
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