56F8156 Просмотр технического описания (PDF) - Freescale Semiconductor

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56F8156

16-bit Digital Signal Controllers

Freescale Semiconductor 

Signal Pins

Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued)

Signal Name Pin No. Type

State

During

Reset

Signal Description

OCR_DIS

VCAP1

VCAP2

VCAP3

VCAP4

VPP1

VPP2

CLKMODE

79

Input

51

Supply

128

83

15

125

Input

2

87

Input

Input

Supply

On-Chip Regulator Disable —

Tie this pin to VSS to enable the on-chip regulator

Tie this pin to VDD to disable the on-chip regulator

This pin is intended to be a static DC signal from power-up to

shut down. Do not try to toggle this pin for power savings

during operation.

VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled),

connect each pin to a 2.2μF or greater bypass capacitor in order to

bypass the core logic voltage regulator, required for proper chip

operation. When OCR_DIS is tied to VDD (regulator disabled),

these pins become VDD_CORE and should be connected to a

regulated 2.5V power supply.

Input

VPP1 - 2 — These pins should be left unconnected as an open

circuit for normal functionality.

Input

Clock Input Mode Selection — This input determines the

function of the XTAL and EXTAL pins.

1 = External clock input on XTAL is used to directly drive the input

clock of the chip. The EXTAL pin should be grounded.

EXTAL

XTAL

0 = A crystal or ceramic resonator should be connected between

XTAL and EXTAL.

82

Input

Input

External Crystal Oscillator Input — This input can be connected

to an 8MHz external crystal. Tie this pin low if XTAL is driven by an

external clock source.

81

Input/ Chip-driven Crystal Oscillator Output — This output connects the internal

Output

crystal oscillator output to an external crystal.

If an external clock is used, XTAL must be used as the input and

EXTAL connected to GND.

CLKO

The input clock can be selected to provide the clock directly to the

core. This input clock can also be selected as the input clock for

the on-chip PLL.

3

Output

In reset, Clock Output — This pin outputs a buffered clock signal. Using

output is the SIM CLKO Select Register (SIM_CLKOSR), this pin can be

disabled programmed as any of the following: disabled, CLK_MSTR

(system clock), IPBus clock, oscillator output, prescaler clock and

postscaler clock. Other signals are also available for test

purposes.

See Part 6.5.7 for details.

56F8356 Technical Data, Rev. 13

Freescale Semiconductor

19

Preliminary

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