56F8156 Просмотр технического описания (PDF) - Freescale Semiconductor

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56F8156

16-bit Digital Signal Controllers

Freescale Semiconductor 

Introduction

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8356 and 56F8156 are organized into functional groups, as detailed

in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals

present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of Pins in Package

56F8356

56F8156

Power (VDD or VDDA)

Power Option Control

Ground (VSS or VSSA)

Supply Capacitors1 & VPP

PLL and Clock

Address Bus

9

9

1

1

6

6

6

6

4

4

17

17

Data Bus

Bus Control

Interrupt and Program Control

Pulse Width Modulator (PWM) Ports

Serial Peripheral Interface (SPI) Port 0

Serial Peripheral Interface (SPI) Port 1

Quadrature Decoder Port 02

16

16

6

6

6

6

25

13

4

4

—

4

4

4

Quadrature Decoder Port 13

Serial Communications Interface (SCI) Ports

CAN Ports

Analog to Digital Converter (ADC) Ports

Quad Timer Module Ports

JTAG/Enhanced On-Chip Emulation (EOnCE)

4

—

4

4

2

—

21

21

3

1

5

5

Temperature Sense

1

—

Dedicated GPIO

—

5

1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs

2. Alternately, can function as Quad Timer pins or GPIO

3. Pins in this section can function as Quad Timer, SPI #1, or GPIO

56F8356 Technical Data, Rev. 13

Freescale Semiconductor

15

Preliminary

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