MC33567D-2 Просмотр технического описания (PDF) - ON Semiconductor
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MC33567D-2 Datasheet PDF : 8 Pages
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MC33567
200
PHASE °
100
GAIN dB
PHASE MARGIN =
48° @ 8 kHz
PHASE MARGIN =
60° @ 200 kHz
200
PHASE °
100
GAIN dB
*PHASE MARGIN =
85° @ 8 kHz
PHASE MARGIN =
48° @ 500 kHz
0
m ILOAD = 2 A
C = 200 F
Resr = 50 mW
–100 101
102
103
104
105
f, FREQUENCY
Figure 2. Gain–Phase Plot @ 50 mW
0
ILOAD = 2 A
C = 200 mF
W Resr = 200 m
106 –100 101
102
103
104
f, FREQUENCY
105
106
Figure 3. Gain–Phase Plot @ 200 mW
*NOTE: For adequate phase margin, C X R ≥ 10 X 10–6.
m W E.g. 200 F X 50 m = 10 X 10–6,
400 mF X 25 mW = 10 X 10–6,
m W 800 F X 12.5 m = 10 X 10–6.
Capacitor Selection Guidelines
The goal here is to preserve adequate phase margin for
stable operation. For adequate phase margin, the load
capacitance ESR value multiplied by the load capacitance
must be greater than 10x10–6. For example, if the load
capacitor is 400µF, then the ESR value of the capacitor
would need to be no less than 25 milliOhms, (400µF x
25mOhm = 10x10–6). Similarly, if the load capacitance was
200µF, then the ESR value of the capacitance would need to
be at least 50 milliOhms, (200µF x 50mOhm = 10x10–6).
(Important Note: The foregoing rule assumes that all
capacitors across the load are of the same type and value. If
different types and values of capacitors are used in parallel
across the load, then each individual capacitors must meet
the C x ESR > 10x10–6 rule).
PIN 5 TRUTH TABLE
Pin 5 No connect = 1.5V LDO drive out active
Pin 5 < 0.8V = shutoff (drive out 0V)
2.5V < pin 5 < 4.1V = 1.5V LDO drive out active
Pin 5 > 4.1V = 3.3V bypass mode (drive out = Vcc)
AGP Card Type
Detection
12Vin
3.3Vin
PCB Layout Guidelines
The goal here is to minimize extraneous signals from
being either magnetically or electrostatically induced on the
sense lines or drive lines. As much as practical, the LDO
control ic should be physically close (short traces) to the
external series pass transistors; the layout of the sense trace
should parallel, go in the same direction, and be on the same
plane as the power trace going from the series pass transistor
source lead to the load; routing the sense lead near the load
current return path should be avoided; unterminated runs of
the sense lead should be avoided (if options on sense lead
destinations are desired on the board, then use zero ohm
resistor jumpers to make the alternate sense lead
connections near the sense pin itself).
AGP Card Voltage
3.3Vin
1.5V/3.3V
R7
10k
1
8
2 1.8V 1.5V 7
3 MC33567 6 Gate 2 drv
4
5 Sense2
Shutoff2
Figure 4. 1.5V/3.3V AGP card detection
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5
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