Quad-Output TFT LCD DC-DC
Converters with Buffer
Pin Description (continued)
MAX1778
MAX1881
14
PIN
MAX1880 MAX1883
MAX1882 MAX1884
−
12
MAX1885
−
NAME
LDOOUT
FUNCTION
Linear Regulator Output. Sources up to 40mA. Bypass to GND with
a ceramic capacitor determined by:
CLDOOUT
≥
0.5ms
X
ILDOOUT(MAX)
VLDOOUT
15
−
13
−
FBL
Voltage Setting Input. Connect a resistive divider from the linear
regulator output (VLDOOUT) to FBL to analog ground (GND).
Fault Trip-Level Set Input. Connect to a resistive divider between
REF and GND to set the main step-up converter’s and positive
16
16
14
14
FLTSET charge pump’s fault thresholds between 0.67 x VREF and 0.85 x
VREF. Connect to GND for the preset fault threshold (0.9 x VREF).
17
17
−
18
18
−
−
SUPN
Negative Charge-Pump Driver Supply Voltage. Bypass to power
ground (PGND) with a 0.1µF capacitor.
−
DRVN
Negative Charge-Pump Driver Output. Output high level is VSUPN
and low level is PGND.
19
19
−
−
SUPP
Positive Charge-Pump Driver Supply Voltage. Bypass to power
ground (PGND) with a 0.1µF capacitor.
20
20
−
−
DRVP
Positive Charge-Pump Driver Output. Output high level is VSUPP
and low level is PGND
21
21
17
17
PGND Power Ground. Connect to analog ground (GND) underneath the
IC.
22
22
18
18
LX
Main Step-Up Regulator Power MOSFET N-Channel Drain. Place
output diode and output capacitor as close to PGND as possible.
23
23
19
19
TGND Must be connected to ground.
24
24
20
20
RDY
Active-Low, Open-Drain Output. Indicates all outputs are ready.
On-resistance is 125Ω (typ).
−
13, 14, 15
15, 16
11, 12, 13,
15, 16
N.C.
No Connection. Not internally connected.
18 ______________________________________________________________________________________