DJLXT971ALE.A4 Просмотр технического описания (PDF) - Intel

Номер в каталоге

Компоненты Описание

производитель

DJLXT971ALE.A4

3.3V Dual-Speed Fast Ethernet PHY Transceiver

Intel 

LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver

Contents

1.0

Pin Assignments ..............................................................................................................................12

2.0

Signal Descriptions ..........................................................................................................................16

3.0

Functional Description.....................................................................................................................21

3.1 Introduction .......................................................................................................................21

3.1.1 Comprehensive Functionality .............................................................................21

3.1.2 OSP™ Architecture ............................................................................................21

3.2 Network Media / Protocol Support....................................................................................22

3.2.1 10/100 Network Interface ...................................................................................22

3.2.1.1 Twisted-Pair Interface ..........................................................................22

3.2.1.2 Fiber Interface.......................................................................................22

3.2.1.3 Fault Detection and Reporting..............................................................23

3.2.2 MII Data Interface...............................................................................................23

3.2.2.1 Increased MII Drive Strength ...............................................................23

3.2.3 Configuration Management Interface .................................................................24

3.2.3.1 MDIO Management Interface ..............................................................24

3.2.3.2 Hardware Control Interface ..................................................................25

3.3 Operating Requirements....................................................................................................26

3.3.1 Power Requirements ...........................................................................................26

3.3.2 Clock Requirements............................................................................................26

3.3.2.1 External Crystal/Oscillator ...................................................................26

3.3.2.2 MDIO Clock .........................................................................................26

3.4 Initialization.......................................................................................................................26

3.4.1 MDIO Control Mode ..........................................................................................26

3.4.2 Hardware Control Mode .....................................................................................27

3.4.3 Reduced Power Modes........................................................................................28

3.4.3.1 Hardware Power Down ........................................................................28

3.4.3.2 Software Power Down..........................................................................29

3.4.3.3 Sleep Mode ...........................................................................................29

3.4.4 Reset....................................................................................................................29

3.4.5 Hardware Configuration Settings........................................................................30

3.5 Establishing Link...............................................................................................................31

3.5.1 Auto-Negotiation ................................................................................................31

3.5.1.1 Base Page Exchange .............................................................................31

3.5.1.2 Next Page Exchange .............................................................................31

3.5.1.3 Controlling Auto-Negotiation...............................................................31

3.5.2 Parallel Detection ................................................................................................31

3.6 MII Operation....................................................................................................................32

3.6.1 MII Clocks ..........................................................................................................32

3.6.2 Transmit Enable ..................................................................................................33

3.6.3 Receive Data Valid .............................................................................................33

3.6.4 Carrier Sense .......................................................................................................33

3.6.5 Error Signals .......................................................................................................33

3.6.6 Collision ..............................................................................................................33

3.6.7 Loopback.............................................................................................................34

3.6.7.1 Operational Loopback ..........................................................................35

Datasheet

3

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

Share Link: