DJLXT971ALE.A4 Просмотр технического описания (PDF) - Intel

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производитель

DJLXT971ALE.A4

3.3V Dual-Speed Fast Ethernet PHY Transceiver

Intel 

LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver

Page

N/A

Revision 001

Revision Date: January 2001

Description

Clock Requirements: Modified language under Clock Requirements heading.

Table 21 I/O Characteristics REFCLK: Changed values for Input Clock Duty Cycle under Min from

40 to 35 and under Max from 60 to 65.

Datasheet

9

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

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