LPC1102UK Просмотр технического описания (PDF) - NXP Semiconductors.
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LPC1102UK Datasheet PDF : 43 Pages
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NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
Table 5. Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
IOH
HIGH-level output
VOH = VDD 0.4 V;
current
2.5 V VDD 3.6 V
1.8 V VDD < 2.5 V
IOL
LOW-level output
VOL = 0.4 V
current
2.5 V VDD 3.6 V
1.8 V VDD < 2.5 V
IOHS
HIGH-level short-circuit VOH = 0 V
output current
IOLS
LOW-level short-circuit VOL = VDD
output current
Ipd
pull-down current
VI = 5 V
Ipu
pull-up current
VI = 0 V;
2.0 V VDD 3.6 V
1.8 V VDD < 2.0 V
VDD < VI < 5 V
External clock input
Vi(xtal)
crystal input voltage
Min
Typ[1]
Max
Unit
4
-
-
mA
3
-
-
mA
4
-
-
mA
3
-
[11] -
-
-
mA
45
mA
[11] -
-
50
mA
10
50
150
A
15
50
85
A
10
50
85
A
0
0
0
A
0.5
1.8
1.95
V
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] Tamb = 25 C.
[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4] IRC enabled; external clock disabled; system PLL disabled.
[5] BOD disabled.
[6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration
block. Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[7] IRC disabled; system oscillator enabled; system PLL enabled.
[8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. Before entering deep-sleep
mode, you must write a 0 to bit 4 and bit 5 of the GPIO0DATA register at location 0x5000 3FFC and a 1 to bit 4 and bit 5 of the
GPIO0DIR register at location 0x5000 8000.
[9] Including voltage on outputs in 3-state mode.
[10] VDD supply voltage must be present.
[11] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
LPC1102_1104
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 26 September 2013
© NXP B.V. 2013. All rights reserved.
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