LPC1102UK Просмотр технического описания (PDF) - NXP Semiconductors.
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LPC1102UK Datasheet PDF : 43 Pages
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NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
its frequency range while the PLL is providing the desired output frequency. The PLL
output frequency must be lower than 100 MHz. The output divider may be set to divide by
2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100 s.
7.14.3 Clock output (LPC1104 only)
The LPC1104 features a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
7.14.4 Wake-up process
The LPC1102/1104 begin operation at power-up by using the 12 MHz IRC oscillator as the
clock source. This allows chip operation to resume quickly. If an external clock or the PLL
is needed by the application, software will need to enable these features and wait for them
to stabilize before they are used as a clock source.
7.14.5 Power control
The LPC1102/1104 support a variety of power control features. There are two special
modes of processor power reduction: Sleep mode and Deep-sleep mode. The CPU clock
rate may also be controlled as needed by changing clock sources, reconfiguring PLL
values, and/or altering the CPU clock divider value. This allows a trade-off of power
versus processing speed based on application requirements. In addition, a register is
provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning
of power consumption by eliminating all dynamic power use in any peripherals that are not
required for the application. Selected peripherals have their own clock divider which
provides even better power control.
7.14.5.1 Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through a simple call to the power profiles. The power configuration routine configures the
LPC1102/1104 for one of the following power modes:
• Default mode corresponding to power configuration after reset.
• CPU performance mode corresponding to optimized processing capability.
• Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profiles includes a routine to select the optimal PLL settings for a
given system clock and PLL input clock.
7.14.5.2 Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
LPC1102_1104
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 26 September 2013
© NXP B.V. 2013. All rights reserved.
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