SAA7165WP Просмотр технического описания (PDF) - Philips Electronics
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SAA7165WP Datasheet PDF : 28 Pages
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Philips Semiconductors
Video Enhancement and Digital-to-Analog
processor (VEDA2)
Product specification
SAA7165
Table 9 Logic levels and function of BFB, WG1 and WG0
DATA BITS
BFB
0
0
0
0
1
1
1
1
WG1
0
0
1
1
0
0
1
1
WG0
0
1
0
1
0
1
0
1
K = 1⁄8; minimum peaking
K = 1⁄4
K = 1⁄2
K = 1; maximum peaking
K = 0; peaking off
K = 1⁄4; minimum peaking
K = 1⁄2
K = 1; maximum peaking
FUNCTION
Table 10 Logic levels and function of IFF, IFC and IFL
DATA BITS
IFF
IFC
IFL
FUNCTION
0
0
0
4 : 1 : 1 format; −3 dB attenuation at 1.6 MHz video frequency; (see Fig.10)
0
0
1
4 : 1 : 1 format; −3 dB attenuation at 600 kHz video frequency; (see Fig.11)
0
1
X
4 : 1 : 1 format; −3 dB attenuation at 1.2 MHz video frequency; (see Fig.12)
1
0
0
4 : 2 : 2 format; −3 dB attenuation at 1.6 MHz video frequency; (see Fig.10)
1
0
1
4 : 2 : 2 format; −3 dB attenuation at 600 kHz video frequency; (see Fig.11)
1
1
X
4 : 2 : 2 format; −3 dB attenuation at 2.5 MHz video frequency; (see Fig.13)
Table 11 Logic levels and function of LI1 and LI0
DATA BITS
LI1
LI0
0
0
0
1
1
0
1
1
RANGE
+4 to −4
+6 to −6
+8 to −8
+12 to −12
Table 12 Logic levels and function of GA1 and GA0
DATA BITS
GA1
0
0
1
1
GA0
0
off
1
1⁄4
0
1⁄2
1
1
FACTOR
Table 13 Logic levels and function of DC1 and DC0
DATA BITS
DC1
0
0
1
1
DC0
0
1
0
1
DELAYED CLOCK
CYCLES
0
+1
−2
−1
1996 Aug 20
11
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