SAA7165WP Просмотр технического описания (PDF) - Philips Electronics
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SAA7165WP Datasheet PDF : 28 Pages
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Philips Semiconductors
Video Enhancement and Digital-to-Analog
processor (VEDA2)
Product specification
SAA7165
RESDAC resolution
ILE
DC integral linearity error
DLE
DC differential error
luminance DAC
−
9
−
bits
chrominance DACs
−
8
−
bits
8-bit data
−
−
1.0
LSB
8-bit data
−
−
0.5
LSB
Y, (R − Y) and (B − Y) analog outputs (pins 33, 36 and 39)
Vo(p-p)
output signal voltage
(peak to peak value)
without load
−
2
−
V33,36,39
V39
V33,36
output voltage range
output blanking level
output no-colour level
without load; note 2
0.2
Y output; note 3
−
±(R − Y), ±(B − Y);
−
note 4
−
2.2
16
−
128
−
R33,36,39
RL33,36,39
B
internal serial output resistance
output load resistance
output signal bandwidth
external load
−3 dB
−
25
−
125
−
−
20
−
−
td
signal delay from input to Y output
−
tbf
−
LCC timing (pin 25) (see Fig.3)
V
V
LSB
LSB
Ω
Ω
MHz
ns
TLLC
tp H
tr
tf
cycle time
pulse width
rise time
fall time
YUV-bus timing (pins 4 to 11 and 14 to 21) (see Fig.5)
27.7
37
41
ns
40
50
60
%
−
−
5
ns
−
−
6
ns
tSU;DAT
tHD;DAT
input data set-up time
input data hold time
MC timing (pin 24) (see Fig.5)
tSU;DAT
tHD;DAT
input data set-up time
input data hold time
RESET timing (pin 27)
10
−
−
ns
3
−
−
ns
10
−
−
ns
3
−
−
ns
tSU
set-up time after power-on or
active LOW; note 5
4 × tLLC −
−
ns
failure
Notes
1. YUV-bus data is read at MC = HIGH (pin 24) clocked with LLC (see Fig.5); data is read only with every second rising
edge of LLC when CREF = 1⁄2LLC on pin 24.
2. 0.2 to 2.2 V output voltage range at 8-bit DAC input data; the data word can increase to 9-bit dependent on peaking
factor.
3. The luminance signal is set to the digital black level: 16 LSB for BLV-bit = 0; 0 LSB for BLV-bit = 1.
4. The chrominance amplitudes are set to the digital colourless level of 128 LSB.
5. The circuit is prepared for a new data initialization.
1996 Aug 20
14
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