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TDA5153

Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads

Philips Electronics 

Philips Semiconductors

Pre-amplifier for Hard Disk Drive (HDD)

with MR-read/inductive write heads

Preliminary specification

TDA5153

A7 A6 A5 A4 A3 A2 A1 A0

DESCRIPTION

0 0 1 1 0 0 1 0 MR current DAC register:

IMR

=

0.5

×





-1--R-0----e-k--x-Ω-t-- 

×

(10 + 16 ⋅ d4 + 8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0)

mA

0 1 0 0 0 0 1 0 write current DAC register:

IWR

=





1---R-0----e-k--x-Ω-t--





×

(20 + 16 ⋅ d4 + 8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0)

mA

0 1 0 1 0 0 1 0 servo write register:

(d0, d1) = (0, 0) = one head

(d0, d1) = (1, 1) = all heads

0 1 1 0 0 0 1 0 test mode register:

(d2,d1,d0) = (0,0,0) = not in test mode

(d2,d1,d0) = (0,0,1) = read head test (IMR1 = IMR2)

(d2,d1,d0) = (0,1,0) = read head test (IMR2 = 5 mA fixed)

(d2,d1,d0) = (0,1,1) = temperature monitor

(d2,d1,d0) = (1, X, d0) = thermal asperity detection

Vth = (210 + 560 ⋅ d0 + 280 ⋅ b2) µV , see note 2

0 1 1 1 0 0 1 0 compensation capacitor register:

equivalent differential capacitance: (4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0) × 2 pF

1 0 0 0 0 0 1 0 high frequency gain attenuator register:

nominal pole frequency: 8-----⋅---d----3-----+-----4-----⋅-8--d-0---2-0---+--M---2--H---⋅-z--d----1-----+-----1-----⋅---d---0--

1 0 0 1 0 0 1 0 high-frequency gain boost register:

nominal zero frequency: 8-----⋅---d----3-----+-----4-----⋅-8--d-0---2-0---+--M---2--H---⋅-z--d----1-----+-----1-----⋅---d---0--

1 0 1 0 0 0 1 0 settle time register:

settle time: tst = 2 + --(--4-----⋅---d----2-----+-----2----⋅---d---1-1-----+-----1-----⋅---d----0----+-----1----)- µs

1 1 1 1 0 0 1 1 chip ID register:

ID = 8 ⋅ d3 + 4 ⋅ d2 + 2 ⋅ d1 + 1 ⋅ d0 , d3 to d0 are preset to (0, 0, 1, 1)

a7 a6 a5 a4 0 0 1 1 when a0 = 1, data from the register with address a7 to a4 is read out on

SDATA

Notes

1. Not used bits in the registers (indicated by X) are don’t care. Default data, initialized at power-up, is zero in all

registers. For VCC < 2.5 V, the register contents are not guaranteed.

2. Vth programming uses both test mode register and compensation capacitor register. d0 in the formula above is the

LSB of the test mode register and b2 is the data bit d2 of the compensation register.

1997 Jul 02

15

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