IDT82P2284BB Просмотр технического описания (PDF) - Integrated Device Technology
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IDT82P2284BB Datasheet PDF : 384 Pages
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IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Name
Type
TSIG[1] / MTSIGA[1] Input
TSIG[2] / MTSIGB[1]
TSIG[3]
TSIG[4]
TSFS[1] / MTSFS
TSFS[2]
TSFS[3]
TSFS[4]
Output / Input
TSCK[1] / MTSCK
TSCK[2]
TSCK[3]
TSCK[4]
Output / Input
Pin No.
F1
E1
G4
F4
K2
J2
H1
G1
L1
K1
J1
H2
Description
TSIG[1:4]: Transmit Side System Signaling for Link 1 ~ 4
The signaling bits are input on these pins. They are located in the lower nibble (b5 ~ b8) and are channel/
timeslot-aligned with the data input on the corresponding TSDn pin.
In Transmit Clock Master mode, TSIGn is sampled on the active edge of the corresponding TSCKn.
In Transmit Clock Slave mode, selected by the TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), TSIGn is sam-
pled on the active edge of the corresponding TSCKn or all four TSIGn are updated on the active edge of
TSCK[1].
MTSIGA[1] / MTSIGB[1]: Multiplexed Transmit Side System Signaling A / B for Link 1 ~ 4
In Transmit Multiplexed mode, selected by the MTSDA bit (b2, T1/J1-010H / b2, E1-010H), the MTSIGA[1] pin
or the MTSIGB[1] pin is used to input the signaling bits. The signaling bits are located in the lower nibble (b5
~ b8) and are channel/timeslot-aligned with the data input on the corresponding MTSDA[1]/MTSDB[1] pin.
Using the byte-interleaved multiplexing scheme, the MTSIGA[1]/MTSIGB[1] pins input the signaling bits for
Link 1 to Link 4. The signaling bits on the MTSIGA[1]/MTSIGB[1] pin is sampled on the active edge of
MTSCK.
TSIG[1:4]/MTSIGA[1]/MTSIGB[1] are Schmitt-triggered inputs.
TSFS[1:4]: Transmit Side System Frame Pulse for Link 1 ~ 4
In T1/J1 Transmit Clock Master mode, TSFSn outputs the pulse to indicate each F-bit or the first F-bit of every
SF/ESF/T1 DM/SLC-96 multi-frame.
In T1/J1 Transmit Clock Slave mode, TSFSn inputs the pulse to indicate each F-bit or the first F-bit of every
SF/ESF/T1 DM/SLC-96 multi-frame.
In E1 Transmit Clock Master mode, TSFSn outputs the pulse to indicate the Basic frame, CRC Multi-frame
and/or Signaling Multi-frame.
In E1 Transmit Clock Slave mode, TSFSn inputs the pulse to indicate the Basic frame, CRC Multi-frame and/
or Signaling Multi-frame.
TSFSn is updated/sampled on the active edge of the corresponding TSCKn. The active polarity of TSFSn is
selected by the FSINV bit (b1, T1/J1-042H,... / b1, E1-042H,...).
MTSFS: Multiplexed Transmit Side System Frame Pulse for Link 1 ~ 4
In T1/J1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each F-bit or the first F-bit of every
SF/ESF/T1 DM/SLC-96 multi-frame of one link on the multiplexed data bus.
In E1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each Basic frame, CRC Multi-frame
and/or Signaling Multi-frame of one link on the multiplexed data bus.
MTSFS is sampled on the active edge of MTSCK. The active polarity of MTSFS is selected by the FSINV bit
(b1, T1/J1-042H,... / b1, E1-042H,...).
TSFS[1:4]/MTSFS are Schmitt-triggered inputs/outputs with pull-up resistors.
TSCK[1:4]: Transmit Side System Clock for Link 1 ~ 4
In Transmit Clock Master mode, TSCKn outputs a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz (for E1
mode) clock used to sample the signal on the corresponding TSDn and TSIGn pins and update the signal on
the corresponding TSFSn pin.
In Transmit Clock Slave mode, TSCKn inputs a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096 MHz
clock used to sample the signal on the corresponding TSDn, TSIGn and TSFSn pins. Selected by the
TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), the TSCK[1] can be used for all four links.
MTSCK: Multiplexed Transmit Side System Clock for Link 1 ~ 4
In Transmit Multiplexed mode, MTSCK inputs a 8.192 MHz or 16.384 MHz clock used to sample the signal on
the corresponding MTSDA/MTSDB, MTSIGA/MTSIGB and MTSFS pins.
TSCK[1:4]/MTSCK are Schmitt-triggered inputs/outputs with pull-up resistors.
Clock Generator
Pin Description
6
March 22, 2004
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