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IDT72V36104

3.3 VOLT CMOS SyncBiFIFO™ WITH BUS-MATCHING

Integrated Device Technology 

IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH

BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant)

Symbol

Parameter

IDT72V3684L10

IDT72V3694L10

IDT72V36104L10

Min.

Max.

IDT72V3684L15

IDT72V3694L15

IDT72V36104L15

Min.

Max. Unit

fS

Clock Frequency, CLKA or CLKB

—

100

—

66.7 MHz

tCLK

Clock Cycle Time, CLKA or CLKB

10

—

15

—

ns

tCLKH

Pulse Duration, CLKA or CLKB HIGH

4.5

—

6

—

ns

tCLKL

Pulse Duration, CLKA and CLKB LOW

4.5

—

6

—

ns

tDS

Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑

3

tENS1

Setup Time, CSA and W/RA before CLKA↑; CSB and

4

W/RB before CLKB↑

—

4

—

4.5

—

ns

—

ns

tENS2

tRSTS

tFSS

tBES

Setup Time, ENA, and MBA before CLKA↑; ENB, and

MBB before CLKB↑

Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before

CLKA↑ or CLKB↑(1)

Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH

Setup Time, BE/FWFT before MRS1 and MRS2 HIGH

3

—

4.5

5

—

5

7.5

—

7.5

7.5

—

7.5

—

ns

—

ns

—

ns

—

ns

tSDS

tSENS

tFWS

tRTMS

Setup Time, FS0/SD before CLKA↑

Setup Time, FS1/SEN before CLKA↑

Setup Time, BE/FWFT before CLKA↑

Setup Time, RTM before RT1; RTM before RT2

3

—

4

3

—

4

0

—

0

5

—

5

—

ns

—

ns

—

ns

—

ns

tDH

Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑

0.5

—

1

tENH

Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB,

W/RB, ENB, and MBB after CLKB↑

0.5

—

1

tRSTH

Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑

4

—

4

or CLKB↑(1)

tFSH

Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH

2

—

2

tBEH

Hold Time, BE/FWFT after MRS1 and MRS2 HIGH

2

—

2

—

ns

—

ns

—

ns

—

ns

—

ns

tSDH

tSENH

tSPH

Hold Time, FS0/SD after CLKA↑

Hold Time, FS1/SEN HIGH after CLKA↑

Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH

0.5

—

1

0.5

—

1

2

—

2

—

ns

—

ns

—

ns

tRTMH

tSKEW1(2)

Hold Time, RTM after RT1; RTM after RT2

Skew Time between CLKA↑ and CLKB↑ for EFA/ORA,

EFB/ORB, FFA/IRA, and FFB/IRB

5

—

5

—

ns

5

—

7.5

—

ns

tSKEW2(2.3) Skew Time between CLKA↑ and CLKB↑ for AEA, AEB, AFA,

12

and AFB

—

12

—

ns

NOTES:

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

3. Design simulated, not tested.

8

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