IDT72V36104 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V36104 Datasheet PDF : 36 Pages
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3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING
16,384 x 36 x 2
IDT72V3684
32,768 x 36 x 2
IDT72V3694
65,536 x 36 x 2
IDT72V36104
FEATURES
• Memory storage capacity:
IDT72V3684 – 16,384 x 36 x 2
IDT72V3694 – 32,768 x 36 x 2
IDT72V36104 – 65,536 x 36 x 2
• Clock frequencies up to 100 MHz (6.5ns access time)
• Two independent clocked FIFOs buffering data in opposite
directions
• Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has five
default offsets (8, 16, 64, 256 and 1,024 )
• Serial or parallel programming of partial flags
• Retransmit Capability
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Big- or Little-Endian format for word and byte bus sizes
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
• Auto power down minimizes power dissipation
• Available in space saving 128-pin Thin Quad Flatpack (TQFP)
• Pin compatible to the lower density parts, IDT72V3624/72V3634/
72V3644/72V3654/72V3664/72V3674
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
FFA/IRA
AFA
FS2
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
RT1
RTM
RT2
36
FIFO1 and
FIFO2
Retransmit
Logic
Mail 1
Register
36
RAM ARRAY
16,384 x 36
36
32,768 x 36
65,536 x 36
FIFO1
Write
Pointer
Read
Pointer
Status Flag
Logic
Programmable Flag
Offset Registers
Timing
Mode
16
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
RAM ARRAY
36 16,384 x 36
36
32,768 x 36
65,536 x 36
MBF2
Mail 2
Register
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MBF1
36
EFB/ORB
AEB
36
FIFO2,
Mail2
Reset
Logic
4677 drw01
Port-B
Control
Logic
FWFT
B0-B35
FFB/IRB
AFB
MRS2
PRS2
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
NOVEMBER 2003
DSC-4677/5
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