H8/3068F Просмотр технического описания (PDF) - Renesas Electronics

Номер в каталоге

Компоненты Описание

производитель

H8/3068F

16-Bit Single-Chip Microcomputer

Renesas Electronics 

6.9.2 Pin States in Idle Cycle........................................................................................ 197

6.10 Bus Arbiter........................................................................................................................ 198

6.10.1 Operation ............................................................................................................. 198

6.11 Register and Pin Input Timing .......................................................................................... 201

6.11.1 Register Write Timing ......................................................................................... 201

6.11.2 BREQ Pin Input Timing ...................................................................................... 202

Section 7 DMA Controller................................................................................................ 203

7.1 Overview........................................................................................................................... 203

7.1.1 Features................................................................................................................ 203

7.1.2 Block Diagram..................................................................................................... 204

7.1.3 Functional Overview............................................................................................ 205

7.1.4 Input/Output Pins................................................................................................. 206

7.1.5 Register Configuration......................................................................................... 207

7.2 Register Descriptions (1) (Short Address Mode).............................................................. 208

7.2.1 Memory Address Registers (MAR) ..................................................................... 208

7.2.2 I/O Address Registers (IOAR)............................................................................. 209

7.2.3 Execute Transfer Count Registers (ETCR).......................................................... 210

7.2.4 Data Transfer Control Registers (DTCR) ............................................................ 211

7.3 Register Descriptions (2) (Full Address Mode) ................................................................ 214

7.3.1 Memory Address Registers (MAR) ..................................................................... 214

7.3.2 I/O Address Registers (IOAR)............................................................................. 214

7.3.3 Execute Transfer Count Registers (ETCR).......................................................... 215

7.3.4 Data Transfer Control Registers (DTCR) ............................................................ 217

7.4 Operation .......................................................................................................................... 223

7.4.1 Overview.............................................................................................................. 223

7.4.2 I/O Mode.............................................................................................................. 225

7.4.3 Idle Mode............................................................................................................. 227

7.4.4 Repeat Mode........................................................................................................ 230

7.4.5 Normal Mode....................................................................................................... 234

7.4.6 Block Transfer Mode ........................................................................................... 237

7.4.7 DMAC Activation................................................................................................ 242

7.4.8 DMAC Bus Cycle................................................................................................ 244

7.4.9 Multiple-Channel Operation ................................................................................ 250

7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 251

7.4.11 NMI Interrupts and DMAC ................................................................................. 252

7.4.12 Aborting a DMAC Transfer................................................................................. 253

7.4.13 Exiting Full Address Mode.................................................................................. 254

7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode ......................... 255

7.5 Interrupts........................................................................................................................... 256

Rev. 3.00 Sep 14, 2005 page xi of xxii

Share Link: