H8/3068F Просмотр технического описания (PDF) - Renesas Electronics
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Компоненты Описание
производитель
H8/3068F Datasheet PDF : 935 Pages
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14.3.2 Pin Connections ................................................................................................... 542
14.3.3 Data Format ......................................................................................................... 544
14.3.4 Register Settings .................................................................................................. 545
14.3.5 Clock.................................................................................................................... 547
14.3.6 Transmitting and Receiving Data ........................................................................ 549
14.4 Usage Notes ...................................................................................................................... 557
Section 15 A/D Converter................................................................................................. 561
15.1 Overview........................................................................................................................... 561
15.1.1 Features................................................................................................................ 561
15.1.2 Block Diagram..................................................................................................... 562
15.1.3 Input Pins............................................................................................................. 563
15.1.4 Register Configuration......................................................................................... 564
15.2 Register Descriptions........................................................................................................ 565
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 565
15.2.2 A/D Control/Status Register (ADCSR) ............................................................... 566
15.2.3 A/D Control Register (ADCR) ............................................................................ 569
15.3 CPU Interface ................................................................................................................... 570
15.4 Operation .......................................................................................................................... 572
15.4.1 Single Mode (SCAN = 0) .................................................................................... 572
15.4.2 Scan Mode (SCAN = 1)....................................................................................... 574
15.4.3 Input Sampling and A/D Conversion Time ......................................................... 576
15.4.4 External Trigger Input Timing............................................................................. 578
15.5 Interrupts........................................................................................................................... 579
15.6 Usage Notes ...................................................................................................................... 579
Section 16 D/A Converter................................................................................................. 585
16.1 Overview........................................................................................................................... 585
16.1.1 Features................................................................................................................ 585
16.1.2 Block Diagram..................................................................................................... 586
16.1.3 Input/Output Pins................................................................................................. 586
16.1.4 Register Configuration......................................................................................... 587
16.2 Register Descriptions........................................................................................................ 588
16.2.1 D/A Data Registers 0 and 1 (DADR0/1) ............................................................. 588
16.2.2 D/A Control Register (DACR) ............................................................................ 588
16.2.3 D/A Standby Control Register (DASTCR).......................................................... 590
16.3 Operation .......................................................................................................................... 591
16.4 D/A Output Control .......................................................................................................... 592
Rev. 3.00 Sep 14, 2005 page xvii of xxii
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