GL811E Просмотр технического описания (PDF) - GENESYS LOGIC
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GL811E Datasheet PDF : 33 Pages
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GL811E USB 2.0 to ATA/ATAPI Bridge Controller
3.2 Pin Descriptions
Table 3.1 - Pin Descriptions
Pin Name
GPIO7
GPIO5~6
IODD[8:11]
DVCC1~2
DGND1~2
IODD[12:15]
CBLID_
CS1_
DA2/SK
RESET#
RPU
AVCC0~1
DPF
DPH
DMF
DMH
AGND0~1
RREF
X2
X1
TEST
CS0_
DA0~1
DA2
INTRQ
DMACK_
IORDY
48Pin# 64 Pin# I/O Type
Description
1
1
B
(tri)
GPIO7 (**)
-
3,4
O AP programmable
2~5 5~8
B
(tri) IDE data bus 8~11 (*****)
6,43 56,9
P Digital VCC
7,42 55,10
8~11 11~14
12
15
13
20
14
-
15
22
16
23
P Digital ground
B
(tri)
IDE data bus 12~15 (*****)
I
(tri)
Cable select input (*****)
O
(tri)
Chip select 1 (*****)
O
(tri)
IDE address 2 / Serial data clock for EEPROM (*****)
I
(pu)
Reset pin (***)
A 3.3v output
17,24 24,31
P Analog VCC
18
25
B Full speed DP
19
26
B High speed DP
20
27
B Full speed DM
21
28
B High speed DM
22,27 29,34
P Analog ground
23
30
A Reference resister connect (****)
25
32
B Crystal output
26
28
29
30,31
-
32
33
34
33
-
37
38,39
21
44
45
46
I Crystal input, 12Mhz
I
(pd)
TEST mode input
O
(tri)
Chip select 0 (*****)
O
(tri)
IDE address 0~1 (*****)
O
(tri)
IDE address 2 (*****)
I
(tri)
IDE interrupt input (*****)
O
(tri)
IDE acknowledge (*****)
I
(pu)
IDE ready (*****)
©2000-2006 Genesys Logic Inc. - All rights reserved.
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