GL811E Просмотр технического описания (PDF) - GENESYS LOGIC

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производитель

GL811E

USB 2.0 to ATA / ATAPI Bridge Controller

GENESYS LOGIC 

6.4.1 Register Transfers

GL811E USB 2.0 to ATA/ATAPI Bridge Controller

Notes:

1. Device address consists of signals CS0_, CS1_ and DA(2:0).

2. Data consists of IODD(7:0).

3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of

whether the cycle is to be extended is made by the host after tA from the assertion of DIOR_ or DIOW_.

The assertion and negation of IORDY are described as following:

3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.

3.2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released

prior to negation and may be asserted for no more than 5 ns before release: no wait generated.

3.3 Device negates IORDY before tA, IORDY is released prior to negation and may be asserted for no

more than 5 ns before release: wait generated. The cycle completes after IORDY is released. For

cycles where a wait is generated and DIOR_ is asserted, the device shall read data on IODD(0:7) for

tRD before asserting IORDY.

4.DMACK_ shall remain negated during a register transfer.

©2000-2006 Genesys Logic Inc. - All rights reserved.

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