LTC1598LCG Просмотр технического описания (PDF) - Linear Technology
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LTC1598LCG
Linear Technology
LTC1598LCG Datasheet PDF : 24 Pages
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LTC1594L/LTC1598L
APPLICATIONS INFORMATION
CSADC
CSMUX
CLK
EN
D1
DIN
D2
D0
DOUT B4 B3 B2 B1 B0
CH0 TO
CH7
ADCIN =
MUXOUT
COM = GND
tsuCS
tsuCS
EN
D1
DON’T CARE
D2
D0
NULL
BIT
B11 B10 B9
B8
B7
B6
B5
B4
B3 B2
B1
B0
tSMPL
tCONV
EN
D1
DON’T CARE
D2
D0
NULL
BIT
B11 B10 B9
B8
B7
B6
B5
B4
B3 B2
B1
B0
tSMPL
tCONV
tON
tON
Figure 5. Use Separate Chip Selects to Maximize Sample Rate
1594L/98L F05
MUXOUT/ADCIN Loop Economizes
Signal Conditioning
The MUXOUT and ADCIN pins of the LTC1594L/LTC1598L
form a very flexible external loop that allows Program-
mable Gain Amplifier (PGA) and/or processing analog
input signals prior to conversion. This loop is also a cost
effective way to perform the conditioning, because only
one circuit is needed instead of one for each channel.
In the Typical Applications section, there are a few
examples illustrating how to use the MUXOUT/ADCIN loop
to form a PGA and to antialias filter several analog inputs.
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 160µA and automatic
shutdown between conversions, the LTC1594L/
LTC1598L achieve extremely low power consumption
over a wide range of sample rates (see Figure 6). The auto
shutdown allows the supply current to drop with reduced
sample rate. Several things must be taken into account to
achieve such a low power consumption.
Shutdown
The LTC1594L/LTC1598L are equipped with automatic
shutdown features. They draw power when the CS pin is
low. The bias circuits and comparator of the ADC powers
down and the reference input becomes high impedance at
the end of each conversion leaving the CLK running to
clock out the LSB first data or zeroes (see Figures 1 and 2).
When the CS pin is high, the ADC powers down completely
14
1000
100
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fCLK = 200kHz
10
1
0.1
1
10
100
SAMPLE FREQUENCY (kHz)
1594L/98L G01
Figure 6. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
leaving the CLK running to clock the input data word into
MUX. If the CS, DIN and CLK are not running rail-to-rail, the
input logic buffers will draw currents. These currents may
be large compared to the typical supply current. To obtain
the lowest supply current, run the CS, DIN and CLK pins
rail-to-rail.
DOUT Loading
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the DOUT pin
can add more than 50µA to the supply current at a 200kHz
clock frequency. An extra 50µA or so of current goes into
charging and discharging the load capacitor. The same
goes for digital lines driven at a high frequency by any
logic. The (C)(V)(f) currents must be evaluated and the
troublesome ones minimized.
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