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FDC37C672

Enhanced Super I/O Controller with Fast IR

SMSC -> Microchip 

Enhanced Super I/O Controller with Fast IR

Datasheet

Chapter 5 Functional Description

5.1

Super I/O Registers

The address map, shown below in Table 5.1, shows the addresses of the different blocks of the Super I/O

immediately after power up. The base addresses of the FDC, serial and parallel ports can be moved via

the configuration registers. Some addresses are used to access more than one register.

5.2

Host Processor Interface

The host processor communicates with the FDC37C672 through a series of read/write registers. The port

addresses for these registers are shown in Table 5.1. Register access is accomplished through

programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are

capable of sinking a minimum of 12 mA.

Table 5.1 - Super I/O Block Addresses

ADDRESS

Base+(0-5) and +(7)

Base+(0-7)

Base1+(0-7)

Base2+(0-7)

Base+(0-3)

Base+(0-7)

Base+(0-3), +(400-402)

Base+(0-7), +(400-402)

60, 64

BLOCK NAME

Floppy Disk

Serial Port Com 1

Serial Port Com 2

Parallel Port

SPP

EPP

ECP

ECP+EPP+SPP

KYBD

LOGICAL

DEVICE

0

4

5

3

7

NOTES

IR Support

Fast IR

Note: Refer to the configuration register descriptions for setting the base address

SMSC FDC37C672

Page 17

PRELIMINARY DATASHEET

Rev. 10-29-03

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